Searched refs:instruction (Results 126 - 150 of 654) sorted by relevance

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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/immutable/instruction/
H A DImmutableInstruction20bc.java32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.formats.Instruction20bc;
59 public static ImmutableInstruction20bc of(Instruction20bc instruction) { argument
60 if (instruction instanceof ImmutableInstruction20bc) {
61 return (ImmutableInstruction20bc)instruction;
64 instruction.getOpcode(),
65 instruction.getVerificationError(),
66 instruction.getReference());
H A DImmutableInstruction21c.java32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction21c;
58 public static ImmutableInstruction21c of(Instruction21c instruction) { argument
59 if (instruction instanceof ImmutableInstruction21c) {
60 return (ImmutableInstruction21c)instruction;
63 instruction.getOpcode(),
64 instruction.getRegisterA(),
65 instruction.getReference());
H A DImmutableInstruction21ih.java32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction21ih;
55 public static ImmutableInstruction21ih of(Instruction21ih instruction) { argument
56 if (instruction instanceof ImmutableInstruction21ih) {
57 return (ImmutableInstruction21ih)instruction;
60 instruction.getOpcode(),
61 instruction.getRegisterA(),
62 instruction.getNarrowLiteral());
H A DImmutableInstruction31c.java32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction31c;
58 public static ImmutableInstruction31c of(Instruction31c instruction) { argument
59 if (instruction instanceof ImmutableInstruction31c) {
60 return (ImmutableInstruction31c)instruction;
63 instruction.getOpcode(),
64 instruction.getRegisterA(),
65 instruction.getReference());
H A DImmutableArrayPayload.java32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.formats.ArrayPayload;
67 public static ImmutableArrayPayload of(ArrayPayload instruction) { argument
68 if (instruction instanceof ImmutableArrayPayload) {
69 return (ImmutableArrayPayload)instruction;
72 instruction.getElementWidth(),
73 instruction.getArrayElements());
H A DImmutablePackedSwitchPayload.java32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.SwitchElement;
38 import org.jf.dexlib2.iface.instruction.formats.PackedSwitchPayload;
63 public static ImmutablePackedSwitchPayload of(PackedSwitchPayload instruction) { argument
64 if (instruction instanceof ImmutablePackedSwitchPayload) {
65 return (ImmutablePackedSwitchPayload)instruction;
68 instruction.getSwitchElements());
H A DImmutableSparseSwitchPayload.java32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.SwitchElement;
38 import org.jf.dexlib2.iface.instruction.formats.SparseSwitchPayload;
62 public static ImmutableSparseSwitchPayload of(SparseSwitchPayload instruction) { argument
63 if (instruction instanceof ImmutableSparseSwitchPayload) {
64 return (ImmutableSparseSwitchPayload)instruction;
67 instruction.getSwitchElements());
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips5.s8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
H A Dinvalid-mips4.s8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
H A Dinvalid-mips3.s8 dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips3-wrong-error.s9 dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
18 sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all...]
H A Dinvalid-mips32r2.s8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
H A Dinvalid-mips32.s8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 jr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 jalr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 jalr.hb $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips2.s8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 mtlo $25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mtlo $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
H A Dinvalid-mips1.s8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
/external/llvm/test/MC/Mips/mips32/
H A Dinvalid-mips32r2.s8 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips1.s8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mtlo $25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
H A Dinvalid-mips32.s8 madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
/external/valgrind/main/none/tests/mips64/
H A Dmacro_fpu.h216 #define TESTINST1s(instruction, RDval) \
225 instruction" end"instruction"s"#RDval "\n\t" \
228 "end"instruction"s"#RDval":" "\n\t" \
237 instruction, outf, fs_f[i], ft_f[i]); \
240 #define TESTINST1d(instruction, RDval) \
249 instruction" end"instruction"d"#RDval "\n\t" \
252 "end"instruction"d"#RDval":" "\n\t" \
261 instruction, out
[all...]
/external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/
H A DInstructionMethodItem.java40 import org.jf.dexlib2.iface.instruction.*;
41 import org.jf.dexlib2.iface.instruction.formats.Instruction20bc;
42 import org.jf.dexlib2.iface.instruction.formats.Instruction31t;
43 import org.jf.dexlib2.iface.instruction.formats.UnknownInstruction;
55 @Nonnull protected final T instruction; field in class:InstructionMethodItem
57 public InstructionMethodItem(@Nonnull MethodDefinition methodDef, int codeAddress, @Nonnull T instruction) { argument
60 this.instruction = instruction;
84 Opcode opcode = instruction.getOpcode();
90 if (instruction instanceo
[all...]
/external/smali/dexlib2/src/main/java/org/jf/dexlib2/dexbacked/raw/
H A DCodeItem.java38 import org.jf.dexlib2.dexbacked.instruction.DexBackedInstruction;
40 import org.jf.dexlib2.iface.instruction.*;
41 import org.jf.dexlib2.iface.instruction.formats.*;
121 Instruction instruction = DexBackedInstruction.readFrom(reader);
123 // if we read past the end of the instruction list
125 out.annotateTo(end, "truncated instruction");
128 switch (instruction.getOpcode().format) {
130 annotateInstruction10x(out, instruction);
133 annotateInstruction35c(out, (Instruction35c)instruction);
136 annotateInstruction3rc(out, (Instruction3rc)instruction);
[all...]
/external/llvm/test/MC/ARM/
H A Ddirective-arch_extension-crc.s18 @ CHECK-V7: error: instruction requires: crc armv8
20 @ CHECK-V7: error: instruction requires: crc armv8
22 @ CHECK-V7: error: instruction requires: crc armv8
25 @ CHECK-V7: error: instruction requires: crc armv8
27 @ CHECK-V7: error: instruction requires: crc armv8
29 @ CHECK-V7: error: instruction requires: crc armv8
39 @ CHECK-V7: error: instruction requires: crc armv8
40 @ CHECK-V8: error: instruction requires: crc arm-mode
42 @ CHECK-V7: error: instruction requires: crc armv8
43 @ CHECK-V8: error: instruction require
[all...]
/external/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5.s8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
/external/llvm/test/MC/Mips/mips5/
H A Dinvalid-mips64r2.s8 clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction require
[all...]
/external/lzma/C/
H A DBraIA64.c29 UInt64 instruction, instNorm; local
35 instruction = 0;
37 instruction += (UInt64)data[i + j + bytePos] << (8 * j);
39 instNorm = instruction >> bitRes;
59 instruction &= (1 << bitRes) - 1;
60 instruction |= (instNorm << bitRes);
62 data[i + j + bytePos] = (Byte)(instruction >> (8 * j));

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