/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
H A D | radeon_mipmap_tree.h | 89 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t); 94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target); 103 radeon_mipmap_tree *radeon_miptree_create(radeonContextPtr rmesa,
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H A D | radeon_texture.c | 51 static void teximage_assign_miptree(radeonContextPtr rmesa, 55 static radeon_mipmap_tree *radeon_miptree_create_for_teximage(radeonContextPtr rmesa, 108 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 teximage_assign_miptree(rmesa, texobj, timage); 222 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 237 if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) { 242 radeon_firevertices(rmesa); 248 *stride = get_texture_image_row_stride(rmesa, texImage->TexFormat, width, 0, texImage->TexObject->Target); 284 static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa, argument 328 radeonContextPtr rmesa local 546 teximage_assign_miptree(radeonContextPtr rmesa, struct gl_texture_object *texObj, struct gl_texture_image *texImage) argument 706 radeon_swrast_map_image(radeonContextPtr rmesa, radeon_texture_image *image) argument 740 radeon_swrast_unmap_image(radeonContextPtr rmesa, radeon_texture_image *image) argument 753 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 769 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 782 radeon_miptree_create_for_teximage(radeonContextPtr rmesa, struct gl_texture_object *texObj, struct gl_texture_image *texImage) argument [all...] |
H A D | radeon_common.h | 65 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) argument 68 rrb = radeon_renderbuffer(rmesa->state.depth.rb); 75 static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) argument 79 rrb = radeon_renderbuffer(rmesa->state.color.rb);
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H A D | radeon_mipmap_tree.c | 99 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target) argument 102 return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align); 107 row_align = rmesa->texture_rect_row_align - 1; 113 row_align = rmesa->texture_row_align - 1; 127 static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt, argument 135 lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target); 145 __func__, rmesa, 159 static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) argument 163 assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); 173 compute_tex_image_offset(rmesa, m 188 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument 367 radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t) argument 543 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local [all...] |
H A D | radeon_span.c | 121 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 radeon_firevertices(rmesa);
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H A D | radeon_fbo.c | 238 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 259 ok = rmesa->vtbl.check_blit(rb->Format, rrb->pitch / rrb->cpp); 277 rrb->map_bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, 281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset, 309 if (radeon_bo_is_referenced_by_cs(rrb->bo, rmesa->cmdbuf.cs)) { 310 radeon_firevertices(rmesa); 313 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) { 418 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 422 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) { 442 ok = rmesa [all...] |
/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | radeon_mipmap_tree.h | 89 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t); 94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target); 103 radeon_mipmap_tree *radeon_miptree_create(radeonContextPtr rmesa,
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H A D | radeon_texture.c | 51 static void teximage_assign_miptree(radeonContextPtr rmesa, 55 static radeon_mipmap_tree *radeon_miptree_create_for_teximage(radeonContextPtr rmesa, 108 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 teximage_assign_miptree(rmesa, texobj, timage); 222 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 237 if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) { 242 radeon_firevertices(rmesa); 248 *stride = get_texture_image_row_stride(rmesa, texImage->TexFormat, width, 0, texImage->TexObject->Target); 284 static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa, argument 328 radeonContextPtr rmesa local 546 teximage_assign_miptree(radeonContextPtr rmesa, struct gl_texture_object *texObj, struct gl_texture_image *texImage) argument 706 radeon_swrast_map_image(radeonContextPtr rmesa, radeon_texture_image *image) argument 740 radeon_swrast_unmap_image(radeonContextPtr rmesa, radeon_texture_image *image) argument 753 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 769 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 782 radeon_miptree_create_for_teximage(radeonContextPtr rmesa, struct gl_texture_object *texObj, struct gl_texture_image *texImage) argument [all...] |
H A D | radeon_common.h | 65 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) argument 68 rrb = radeon_renderbuffer(rmesa->state.depth.rb); 75 static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) argument 79 rrb = radeon_renderbuffer(rmesa->state.color.rb);
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H A D | r200_vertprog.c | 105 r200ContextPtr rmesa = R200_CONTEXT( ctx ); local 106 GLfloat *fcmd = (GLfloat *)&rmesa->hw.vpp[0].cmd[VPP_CMD_0 + 1]; 112 R200_STATECHANGE( rmesa, vpp[0] ); 113 R200_STATECHANGE( rmesa, vpp[1] ); 139 fcmd = (GLfloat *)&rmesa->hw.vpp[1].cmd[VPP_CMD_0 + 1]; 143 rmesa->hw.vpp[0].cmd_size = 145 tmp.i = rmesa->hw.vpp[0].cmd[VPP_CMD_0]; 147 rmesa->hw.vpp[0].cmd[VPP_CMD_0] = tmp.i; 149 rmesa->hw.vpp[1].cmd_size = 1 + 4 * (paramList->NumParameters - 96); 150 tmp.i = rmesa 1118 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 1199 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 1240 r200ContextPtr rmesa = R200_CONTEXT(ctx); local [all...] |
H A D | radeon_mipmap_tree.c | 99 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target) argument 102 return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align); 107 row_align = rmesa->texture_rect_row_align - 1; 113 row_align = rmesa->texture_row_align - 1; 127 static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt, argument 135 lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target); 145 __func__, rmesa, 159 static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) argument 163 assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); 173 compute_tex_image_offset(rmesa, m 188 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument 367 radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t) argument 543 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local [all...] |
H A D | radeon_span.c | 121 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 radeon_firevertices(rmesa);
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H A D | radeon_fbo.c | 238 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 259 ok = rmesa->vtbl.check_blit(rb->Format, rrb->pitch / rrb->cpp); 277 rrb->map_bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, 281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset, 309 if (radeon_bo_is_referenced_by_cs(rrb->bo, rmesa->cmdbuf.cs)) { 310 radeon_firevertices(rmesa); 313 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) { 418 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 422 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) { 442 ok = rmesa [all...] |
/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_mipmap_tree.h | 89 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t); 94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target); 103 radeon_mipmap_tree *radeon_miptree_create(radeonContextPtr rmesa,
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H A D | radeon_texture.c | 51 static void teximage_assign_miptree(radeonContextPtr rmesa, 55 static radeon_mipmap_tree *radeon_miptree_create_for_teximage(radeonContextPtr rmesa, 108 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 teximage_assign_miptree(rmesa, texobj, timage); 222 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 237 if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) { 242 radeon_firevertices(rmesa); 248 *stride = get_texture_image_row_stride(rmesa, texImage->TexFormat, width, 0, texImage->TexObject->Target); 284 static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa, argument 328 radeonContextPtr rmesa local 546 teximage_assign_miptree(radeonContextPtr rmesa, struct gl_texture_object *texObj, struct gl_texture_image *texImage) argument 706 radeon_swrast_map_image(radeonContextPtr rmesa, radeon_texture_image *image) argument 740 radeon_swrast_unmap_image(radeonContextPtr rmesa, radeon_texture_image *image) argument 753 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 769 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 782 radeon_miptree_create_for_teximage(radeonContextPtr rmesa, struct gl_texture_object *texObj, struct gl_texture_image *texImage) argument [all...] |
H A D | radeon_common.h | 65 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) argument 68 rrb = radeon_renderbuffer(rmesa->state.depth.rb); 75 static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) argument 79 rrb = radeon_renderbuffer(rmesa->state.color.rb);
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H A D | radeon_mipmap_tree.c | 99 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target) argument 102 return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align); 107 row_align = rmesa->texture_rect_row_align - 1; 113 row_align = rmesa->texture_row_align - 1; 127 static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt, argument 135 lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target); 145 __func__, rmesa, 159 static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) argument 163 assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); 173 compute_tex_image_offset(rmesa, m 188 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument 367 radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t) argument 543 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local [all...] |
H A D | radeon_span.c | 121 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 radeon_firevertices(rmesa);
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H A D | radeon_fbo.c | 238 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 259 ok = rmesa->vtbl.check_blit(rb->Format, rrb->pitch / rrb->cpp); 277 rrb->map_bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, 281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset, 309 if (radeon_bo_is_referenced_by_cs(rrb->bo, rmesa->cmdbuf.cs)) { 310 radeon_firevertices(rmesa); 313 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) { 418 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 422 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) { 442 ok = rmesa [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
H A D | radeon_texture.c | 51 static void teximage_assign_miptree(radeonContextPtr rmesa, 55 static radeon_mipmap_tree *radeon_miptree_create_for_teximage(radeonContextPtr rmesa, 108 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 teximage_assign_miptree(rmesa, texobj, timage); 222 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 237 if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) { 242 radeon_firevertices(rmesa); 248 *stride = get_texture_image_row_stride(rmesa, texImage->TexFormat, width, 0, texImage->TexObject->Target); 284 static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa, argument 328 radeonContextPtr rmesa local 546 teximage_assign_miptree(radeonContextPtr rmesa, struct gl_texture_object *texObj, struct gl_texture_image *texImage) argument 706 radeon_swrast_map_image(radeonContextPtr rmesa, radeon_texture_image *image) argument 740 radeon_swrast_unmap_image(radeonContextPtr rmesa, radeon_texture_image *image) argument 753 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 769 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 782 radeon_miptree_create_for_teximage(radeonContextPtr rmesa, struct gl_texture_object *texObj, struct gl_texture_image *texImage) argument [all...] |
H A D | radeon_common.h | 65 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) argument 68 rrb = radeon_renderbuffer(rmesa->state.depth.rb); 75 static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) argument 79 rrb = radeon_renderbuffer(rmesa->state.color.rb);
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H A D | r200_vertprog.c | 105 r200ContextPtr rmesa = R200_CONTEXT( ctx ); local 106 GLfloat *fcmd = (GLfloat *)&rmesa->hw.vpp[0].cmd[VPP_CMD_0 + 1]; 112 R200_STATECHANGE( rmesa, vpp[0] ); 113 R200_STATECHANGE( rmesa, vpp[1] ); 139 fcmd = (GLfloat *)&rmesa->hw.vpp[1].cmd[VPP_CMD_0 + 1]; 143 rmesa->hw.vpp[0].cmd_size = 145 tmp.i = rmesa->hw.vpp[0].cmd[VPP_CMD_0]; 147 rmesa->hw.vpp[0].cmd[VPP_CMD_0] = tmp.i; 149 rmesa->hw.vpp[1].cmd_size = 1 + 4 * (paramList->NumParameters - 96); 150 tmp.i = rmesa 1118 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 1199 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 1240 r200ContextPtr rmesa = R200_CONTEXT(ctx); local [all...] |
H A D | radeon_mipmap_tree.c | 99 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target) argument 102 return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align); 107 row_align = rmesa->texture_rect_row_align - 1; 113 row_align = rmesa->texture_row_align - 1; 127 static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt, argument 135 lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target); 145 __func__, rmesa, 159 static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) argument 163 assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); 173 compute_tex_image_offset(rmesa, m 188 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument 367 radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t) argument 543 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local [all...] |
H A D | radeon_span.c | 121 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 radeon_firevertices(rmesa);
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H A D | radeon_fbo.c | 238 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 259 ok = rmesa->vtbl.check_blit(rb->Format, rrb->pitch / rrb->cpp); 277 rrb->map_bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, 281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset, 309 if (radeon_bo_is_referenced_by_cs(rrb->bo, rmesa->cmdbuf.cs)) { 310 radeon_firevertices(rmesa); 313 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) { 418 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 422 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) { 442 ok = rmesa [all...] |