Searched refs:v7 (Results 26 - 50 of 162) sorted by relevance

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/external/libunwind/tests/
H A Dppc64-test-altivec.c37 register vector signed int v7; local
129 v7 =
166 printf ("v7 - ");
167 vec_print (v7);
/external/libhevc/common/arm64/
H A Dihevc_inter_pred_filters_luma_vert.s173 ld1 {v7.8b},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
178 umlsl v19.8h, v7.8b, v29.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)//
202 umlal v20.8h, v7.8b, v28.8b //mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)//
219 umlsl v21.8h, v7.8b, v27.8b
234 umlal v30.8h, v7.8b, v26.8b
241 ld1 {v7.8b},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
274 umlsl v19.8h, v7.8b, v29.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)//
298 umlal v20.8h, v7.8b, v28.8b //mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)//
322 umlsl v21.8h, v7.8b, v27.8b
347 umlal v30.8h, v7
[all...]
H A Dihevc_inter_pred_filters_luma_vert_w16out.s130 ld1 {v7.8b},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
135 umlsl v19.8h, v7.8b, v29.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)//
159 umlal v20.8h, v7.8b, v28.8b //mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)//
173 umlsl v21.8h, v7.8b, v27.8b
188 umlal v30.8h, v7.8b, v26.8b
195 ld1 {v7.8b},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
230 umlsl v19.8h, v7.8b, v29.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)//
253 umlal v20.8h, v7.8b, v28.8b //mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)//
277 umlsl v21.8h, v7.8b, v27.8b
299 umlal v30.8h, v7
[all...]
H A Dihevc_intra_pred_luma_mode_3_to_9.s183 sub v7.8b, v28.8b , v6.8b //32-fract
190 umull v24.8h, v12.8b, v7.8b //mul (row 0)
200 umull v22.8h, v16.8b, v7.8b //mul (row 1)
211 umull v20.8h, v14.8b, v7.8b //mul (row 2)
222 umull v18.8h, v23.8b, v7.8b //mul (row 3)
233 umull v24.8h, v12.8b, v7.8b //mul (row 4)
244 umull v22.8h, v16.8b, v7.8b //mul (row 5)
255 umull v20.8h, v14.8b, v7.8b //mul (row 6)
259 umull v18.8h, v23.8b, v7.8b //mul (row 7)
317 umull v20.8h, v14.8b, v7
[all...]
H A Dihevc_itrans_recon_4x4_ttype1.s150 smull v7.4s, v0.4h, v4.4h[2] // 74 * pi2_src[0]
151 smlsl v7.4s, v2.4h, v4.4h[2] // 74 * pi2_src[0] - 74 * pi2_src[2]
152 smlal v7.4s, v3.4h, v4.4h[2] //pi2_out[2] = 74 * pi2_src[0] - 74 * pi2_src[2] + 74 * pi2_src[3]
161 sqrshrn v30.4h, v7.4s,#shift_stage1_idct // (pi2_out[2] + rounding ) >> shift_stage1_idct
193 smull v7.4s, v21.4h, v4.4h[2] // 74 * pi2_src[0]
194 smlsl v7.4s, v16.4h, v4.4h[2] // 74 * pi2_src[0] - 74 * pi2_src[2]
195 smlal v7.4s, v17.4h, v4.4h[2] //pi2_out[2] = 74 * pi2_src[0] - 74 * pi2_src[2] + 74 * pi2_src[3]
205 sqrshrn v30.4h, v7.4s,#shift_stage2_idct // (pi2_out[2] + rounding ) >> shift_stage1_idct
H A Dihevc_intra_pred_luma_mode2.s138 ld1 {v7.8b},[x10],x8
154 rev64 v23.8b, v7.8b
200 ld1 {v7.8b},[x10],x8
226 rev64 v23.8b, v7.8b
265 rev64 v7.8b, v6.8b
267 st1 {v7.s}[0],[x7]
H A Dihevc_inter_pred_filters_luma_vert_w16inp.s164 ld1 {v7.4h},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
167 smlal v19.4s, v7.4h, v29.4h //mul_res1 = vmlal_u8(mul_res1, src_tmp4, coeffabs_7)//
183 smlal v20.4s, v7.4h, v28.4h //mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)//
195 smlal v21.4s, v7.4h, v27.4h
207 smlal v30.4s, v7.4h, v26.4h
214 ld1 {v7.4h},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
239 smlal v19.4s, v7.4h, v29.4h //mul_res1 = vmlal_u8(mul_res1, src_tmp4, coeffabs_7)//
254 smlal v20.4s, v7.4h, v28.4h //mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)//
276 smlal v21.4s, v7.4h, v27.4h
296 smlal v30.4s, v7
[all...]
H A Dihevc_inter_pred_luma_vert_w16inp_w16out.s175 ld1 {v7.4h},[x3],x2 //src_tmp4 = ld1_u8(pu1_src_tmp)//
178 smlal v19.4s,v7.4h,v29.4h //mul_res1 = smlal_u8(mul_res1, src_tmp4, coeffabs_7)//
194 smlal v20.4s,v7.4h,v28.4h //mul_res2 = smlal_u8(mul_res2, src_tmp4, coeffabs_6)//
206 smlal v21.4s,v7.4h,v27.4h
219 smlal v31.4s,v7.4h,v26.4h
226 ld1 {v7.4h},[x3],x2 //src_tmp4 = ld1_u8(pu1_src_tmp)//
253 smlal v19.4s,v7.4h,v29.4h //mul_res1 = smlal_u8(mul_res1, src_tmp4, coeffabs_7)//
269 smlal v20.4s,v7.4h,v28.4h //mul_res2 = smlal_u8(mul_res2, src_tmp4, coeffabs_6)//
292 smlal v21.4s,v7.4h,v27.4h
313 smlal v31.4s,v7
[all...]
H A Dihevc_intra_pred_chroma_mode2.s133 ld2 {v6.8b, v7.8b},[x10],x8
153 rev64 v23.8b, v7.8b
195 ld2 {v6.8b, v7.8b},[x10],x8
223 rev64 v23.8b, v7.8b
297 rev64 v7.8b, v7.8b
298 zip1 v6.8b, v6.8b, v7.8b
299 zip2 v7.8b, v6.8b, v7.8b
H A Dihevc_intra_pred_chroma_mode_3_to_9.s180 sub v7.8b, v28.8b , v6.8b //32-fract
189 umull v24.8h, v25.8b, v7.8b //mul (row 0)
199 umull v22.8h, v16.8b, v7.8b //mul (row 1)
210 umull v20.8h, v14.8b, v7.8b //mul (row 2)
221 umull v18.8h, v19.8b, v7.8b //mul (row 3)
232 umull v24.8h, v25.8b, v7.8b //mul (row 4)
245 umull v22.8h, v16.8b, v7.8b //mul (row 5)
256 umull v20.8h, v14.8b, v7.8b //mul (row 6)
260 umull v18.8h, v19.8b, v7.8b //mul (row 7)
323 umull v20.8h, v14.8b, v7
[all...]
H A Dihevc_intra_pred_filters_chroma_mode_11_to_17.s301 sub v7.8b, v28.8b , v6.8b //32-fract
311 umull v24.8h, v12.8b, v7.8b //mul (row 0)
321 umull v22.8h, v16.8b, v7.8b //mul (row 1)
332 umull v20.8h, v14.8b, v7.8b //mul (row 2)
343 umull v18.8h, v23.8b, v7.8b //mul (row 3)
354 umull v24.8h, v12.8b, v7.8b //mul (row 4)
367 umull v22.8h, v16.8b, v7.8b //mul (row 5)
378 umull v20.8h, v14.8b, v7.8b //mul (row 6)
382 umull v18.8h, v23.8b, v7.8b //mul (row 7)
448 umull v20.8h, v14.8b, v7
[all...]
H A Dihevc_itrans_recon_8x8.s191 ld1 {v7.4h},[x9],#8
200 smlal v24.4s, v7.4h, v0.4h[3] //// y1 * cos1 + y3 * cos3(part of b0)
202 smlsl v26.4s, v7.4h, v1.4h[3] //// y1 * cos3 - y3 * sin1(part of b1)
204 smlsl v28.4s, v7.4h, v0.4h[1] //// y1 * sin3 - y3 * cos1(part of b2)
206 smlsl v30.4s, v7.4h, v1.4h[1] //// y1 * sin1 - y3 * sin3(part of b3)
273 sqrshrn v7.4h, v26.4s,#shift_stage1_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
290 ld1 {v7.4h},[x9],#8
309 smlal v24.4s, v7.4h, v0.4h[3] //// y1 * cos1 + y3 * cos3(part of b0)
310 smlsl v26.4s, v7.4h, v1.4h[3] //// y1 * cos3 - y3 * sin1(part of b1)
311 smlsl v28.4s, v7
[all...]
H A Dihevc_intra_pred_filters_luma_mode_11_to_17.s303 sub v7.8b, v28.8b , v6.8b //32-fract
310 umull v24.8h, v12.8b, v7.8b //mul (row 0)
320 umull v22.8h, v16.8b, v7.8b //mul (row 1)
331 umull v20.8h, v14.8b, v7.8b //mul (row 2)
342 umull v18.8h, v23.8b, v7.8b //mul (row 3)
353 umull v24.8h, v12.8b, v7.8b //mul (row 4)
364 umull v22.8h, v16.8b, v7.8b //mul (row 5)
375 umull v20.8h, v14.8b, v7.8b //mul (row 6)
379 umull v18.8h, v23.8b, v7.8b //mul (row 7)
438 umull v20.8h, v14.8b, v7
[all...]
H A Dihevc_intra_pred_chroma_planar.s156 mov v7.8b, v5.8b //mov #1 to d7 to used for inc for row+1 and dec for nt-1-row
202 add v18.8b, v5.8b , v7.8b //row++ [(row+1)++]c
206 sub v19.8b, v6.8b , v7.8b //[nt-1-row]--
224 add v5.8b, v18.8b , v7.8b //row++ [(row+1)++]
226 sub v6.8b, v19.8b , v7.8b //[nt-1-row]--
246 add v18.8b, v5.8b , v7.8b //row++ [(row+1)++]c
248 sub v19.8b, v6.8b , v7.8b //[nt-1-row]--
272 add v5.8b, v18.8b , v7.8b //row++ [(row+1)++]
274 sub v6.8b, v19.8b , v7.8b //[nt-1-row]--
318 mov v7
[all...]
H A Dihevc_inter_pred_luma_copy_w16out.s165 ld1 {v7.8b},[x6],x2 //vld1_u8(pu1_src_tmp)
169 uxtl v22.8h, v7.8b //vmovl_u8(vld1_u8(pu1_src_tmp)
181 ld1 {v7.8b},[x6],x2 //vld1_u8(pu1_src_tmp)
207 uxtl v22.8h, v7.8b //vmovl_u8(vld1_u8(pu1_src_tmp)
224 ld1 {v7.8b},[x6],x2 //vld1_u8(pu1_src_tmp)
249 uxtl v22.8h, v7.8b //vmovl_u8(vld1_u8(pu1_src_tmp)
H A Dihevc_intra_pred_luma_mode_18_34.s145 ld1 {v7.8b},[x8],x6
174 st1 {v7.8b},[x10],x3
186 ld1 {v7.8b},[x8],x6
216 st1 {v7.8b},[x10],x3
227 ld1 {v7.8b},[x8],x6
249 st1 {v7.8b},[x10],x3
H A Dihevc_itrans_recon_32x32.s173 ld1 {v4.4h, v5.4h, v6.4h, v7.4h},[x14],#32
259 smlsl v30.4s, v14.4h, v7.4h[1]
264 smlsl v28.4s, v15.4h, v7.4h[1]
273 smlal v16.4s, v13.4h, v7.4h[2]
274 smlal v18.4s, v12.4h, v7.4h[0]
292 smlsl v26.4s, v9.4h, v7.4h[3] //// y1 * cos3 - y3 * sin1(part of b1)
305 smlal v22.4s, v11.4h, v7.4h[2]
344 smlsl v22.4s, v12.4h, v7.4h[0]
349 smlal v18.4s, v13.4h, v7.4h[2]
369 smlsl v28.4s, v9.4h, v7
[all...]
/external/chromium_org/third_party/libvpx/source/libvpx/vp8/common/ppc/
H A Dvariance_altivec.asm39 vspltisw v7, 0 ;# zero for merging
54 vmrghb v2, v7, v4
55 vmrghb v3, v7, v5
59 vmrglb v2, v7, v4
60 vmrglb v3, v7, v5
86 vsumsws v8, v8, v7
87 vsumsws v9, v9, v7
130 vsumsws v8, v8, v7
131 vsumsws v9, v9, v7
223 vsumsws v9, v9, v7
[all...]
H A Dvariance_subpixel_altivec.asm253 load_and_align_16 v7, r7, r8, 1
259 vmrghb v3, v6, v7
306 hfilter_8 v7, v10, v11, 1
328 load_and_align_16 v7, r3, r4, 1
346 vfilter_16 v6, v7
347 vfilter_16 v7, v8
358 vmrghb v3, v6, v7
363 load_and_align_16 v7, r7, r8, 1
370 vmrghb v5, v6, v7
372 vmrghb v7, v1
[all...]
/external/libvpx/libvpx/vp8/common/ppc/
H A Dvariance_altivec.asm39 vspltisw v7, 0 ;# zero for merging
54 vmrghb v2, v7, v4
55 vmrghb v3, v7, v5
59 vmrglb v2, v7, v4
60 vmrglb v3, v7, v5
86 vsumsws v8, v8, v7
87 vsumsws v9, v9, v7
130 vsumsws v8, v8, v7
131 vsumsws v9, v9, v7
223 vsumsws v9, v9, v7
[all...]
H A Dvariance_subpixel_altivec.asm253 load_and_align_16 v7, r7, r8, 1
259 vmrghb v3, v6, v7
306 hfilter_8 v7, v10, v11, 1
328 load_and_align_16 v7, r3, r4, 1
346 vfilter_16 v6, v7
347 vfilter_16 v7, v8
358 vmrghb v3, v6, v7
363 load_and_align_16 v7, r7, r8, 1
370 vmrghb v5, v6, v7
372 vmrghb v7, v1
[all...]
/external/chromium_org/third_party/libvpx/source/libvpx/vp8/encoder/ppc/
H A Dfdct_altivec.asm66 vsraw v10, v10, v7 ;# v10 = A0 A1 B0 B1
70 vsraw v11, v11, v7 ;# v11 = A2 A3 B2 B3
84 vsraw v10, v8, v7
90 vsraw v8, v8, v7
115 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
126 vspltisw v7, -16 ;# == 16 == -16, only low 5 bits matter
144 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
155 vspltisw v7, -16 ;# == 16 == -16, only low 5 bits matter
167 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
177 vspltisw v7,
[all...]
/external/chromium_org/ui/views/
H A Dview_unittest_aura.cc59 // +-- v7
82 View* v7 = CreateViewWithLayer(gfx::Rect(0, 4, 100, 104), "v7"); local
83 ui::Layer* v7_layer = v7->layer();
84 w1->GetRootView()->AddChildView(v7);
88 v7->AddChildView(v8);
92 v7->AddChildView(v9);
108 ASSERT_EQ("v1 v4 w2 v7", ui::test::ChildLayerNamesAsString(*w1_layer));
122 ASSERT_EQ("v1 v4 w2 v7", ui::test::ChildLayerNamesAsString(*w1_layer));
148 ASSERT_EQ("v1 v4 w2 v7", u
[all...]
/external/libvpx/libvpx/vp8/encoder/ppc/
H A Dfdct_altivec.asm66 vsraw v10, v10, v7 ;# v10 = A0 A1 B0 B1
70 vsraw v11, v11, v7 ;# v11 = A2 A3 B2 B3
84 vsraw v10, v8, v7
90 vsraw v8, v8, v7
115 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
126 vspltisw v7, -16 ;# == 16 == -16, only low 5 bits matter
144 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
155 vspltisw v7, -16 ;# == 16 == -16, only low 5 bits matter
167 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
177 vspltisw v7,
[all...]
/external/llvm/test/MC/ARM/
H A Ddirective-arch-armv7.s23 @ CHECK-ATTR: Description: ARM v7

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