/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 523 const TargetRegisterClass *RC; local 534 RC = &AArch64::GPR32RegClass; 539 RC = &AArch64::GPR32RegClass; 544 RC = &AArch64::GPR32RegClass; 549 RC = &AArch64::GPR64RegClass; 554 RC = TLI.getRegClassFor(VT); 559 RC = TLI.getRegClassFor(VT); 578 ResultReg = createResultReg(RC);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 1612 const TargetRegisterClass *RC = &ARM::GPRRegClass; local 1613 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1614 RC->getAlignment(),
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H A D | ARMFastISel.cpp | 109 const TargetRegisterClass *RC, 112 const TargetRegisterClass *RC, 116 const TargetRegisterClass *RC, 121 const TargetRegisterClass *RC, 125 const TargetRegisterClass *RC, 130 const TargetRegisterClass *RC, 287 const TargetRegisterClass *RC, 289 unsigned ResultReg = createResultReg(RC); 309 const TargetRegisterClass *RC, 312 unsigned ResultReg = createResultReg(RC); 286 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 308 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 336 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 368 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 394 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 424 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument 521 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local 581 const TargetRegisterClass *RC = isThumb2 ? local 715 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); local 888 const TargetRegisterClass *RC = isThumb2 ? local 963 const TargetRegisterClass *RC; local 1495 const TargetRegisterClass *RC = isThumb2 ? local 1666 const TargetRegisterClass *RC; local 2480 const TargetRegisterClass *RC; local 2677 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; local 3040 const TargetRegisterClass *RC = &ARM::rGPRRegClass; local [all...] |
H A D | ARMISelDAGToDAG.cpp | 3356 unsigned RC; local 3357 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC); 3358 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
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H A D | ARMBaseInstrInfo.cpp | 798 const TargetRegisterClass *RC, 812 switch (RC->getSize()) { 814 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 818 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 826 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 830 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 851 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 868 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 888 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 796 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 987 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 766 const TargetRegisterClass *RC = MRI->getRegClass(R); local 769 if (!SR && RC == &Hexagon::DoubleRegsRegClass) 1234 const TargetRegisterClass *RC = MRI->getRegClass(R); local 1235 unsigned NewR = MRI->createVirtualRegister(RC); 1465 const TargetRegisterClass *RC = MRI->getRegClass(PR); local 1466 unsigned NewPR = MRI->createVirtualRegister(RC);
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H A D | HexagonISelDAGToDAG.cpp | 1232 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI, *MF); local 1234 if (RC == &Hexagon::IntRegsRegClass || 1235 RC == &Hexagon::DoubleRegsRegClass) { 1237 } else if (RC == &Hexagon::PredRegsRegClass) { 1242 } else if (!RC && (dyn_cast<ConstantSDNode>(Arg) != nullptr)) {
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H A D | HexagonInstrInfo.cpp | 475 const TargetRegisterClass *RC, 490 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { 494 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { 498 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { 512 const TargetRegisterClass *RC, 522 const TargetRegisterClass *RC, 535 if (RC == &Hexagon::IntRegsRegClass) { 538 } else if (RC == &Hexagon::DoubleRegsRegClass) { 541 } else if (RC == &Hexagon::PredRegsRegClass) { 552 const TargetRegisterClass *RC, 473 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 508 storeRegToAddr( MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 520 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 550 loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 1041 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg()); local [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 665 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 667 DenseMap<unsigned, unsigned> &RegMap = VRegMapping[RC]; 673 if (RC == &NVPTX::Int1RegsRegClass) { 675 } else if (RC == &NVPTX::Int16RegsRegClass) { 677 } else if (RC == &NVPTX::Int32RegsRegClass) { 679 } else if (RC == &NVPTX::Int64RegsRegClass) { 681 } else if (RC == &NVPTX::Float32RegsRegClass) { 683 } else if (RC == &NVPTX::Float64RegsRegClass) { 895 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 900 VRegRCMap::const_iterator I = VRegMapping.find(RC); 2001 const TargetRegisterClass *RC = MRI->getRegClass(vr); local 2020 const TargetRegisterClass *RC = TRI->getRegClass(i); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 112 const TargetRegisterClass *RC, 116 const TargetRegisterClass *RC, 119 const TargetRegisterClass *RC, 146 const TargetRegisterClass *RC, bool IsZExt = true, 158 const TargetRegisterClass *RC); 160 const TargetRegisterClass *RC); 428 const TargetRegisterClass *RC, 434 // Otherwise, RC is the register class to use. If the result of the 442 (RC ? RC 427 PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, const TargetRegisterClass *RC, bool IsZExt, unsigned FP64LoadOpc) argument 557 const TargetRegisterClass *RC = local 573 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); local 908 const TargetRegisterClass *RC = &PPC::F8RCRegClass; local 969 const TargetRegisterClass *RC = &PPC::F8RCRegClass; local 1013 const TargetRegisterClass *RC = local 1101 const TargetRegisterClass *RC = local 1262 const TargetRegisterClass *RC = local 1274 const TargetRegisterClass *RC = local 1585 const TargetRegisterClass *RC = local 1594 const TargetRegisterClass *RC = local 1747 const TargetRegisterClass *RC = local 1866 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass; local 1921 PPCMaterialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument 1953 PPCMaterialize64BitInt(int64_t Imm, const TargetRegisterClass *RC) argument 2025 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : local 2198 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : local 2217 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 2237 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill) argument 2250 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument [all...] |
H A D | PPCInstrInfo.cpp | 601 const TargetRegisterClass *RC = local 603 if (!RC) 607 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && 608 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && 609 !PPC::G8RCRegClass.hasSubClassEq(RC) && 610 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) 637 const TargetRegisterClass *RC = local 639 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 641 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || 642 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); 772 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument 850 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 885 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument 945 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 1246 const TargetRegisterClass *RC = RCs[c]; local 1889 IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, MachineRegisterInfo &MRI) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); local 426 Reg = MF.addLiveIn(Reg, RC); 439 Reg = MF.addLiveIn(Reg, RC); 1319 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op); local 1320 if (!RC) { 1323 return TRI->getRegClass(RegClass)->hasSubClassEq(RC); 1351 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32); local 1353 Operand.getValueType(), Operand, RC); 1608 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32); local 1611 SDValue(Node, 0), RC); 1663 const TargetRegisterClass *RC; local 1713 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument [all...] |
H A D | SIInstrInfo.cpp | 189 const TargetRegisterClass *RC, 197 if (RI.hasVGPRs(RC)) { 202 } else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) { 210 } else if (RI.isSGPRClass(RC)) { 217 unsigned NumSubRegs = RC->getSize() / 4; 223 switch (RC->getSize() * 8) { 242 const TargetRegisterClass *RC, 248 if (RI.hasVGPRs(RC)) { 253 } else if (RI.isSGPRClass(RC)){ 255 switch(RC 185 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 239 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 590 const TargetRegisterClass *RC = RI.getRegClass(RegClass); local 763 const TargetRegisterClass *RC = RI.getRegClass(RCID); local 826 split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist, MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineOperand &Op) const argument 935 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; local [all...] |
H A D | AMDGPUISelLowering.cpp | 2091 const TargetRegisterClass *RC, 2097 VirtualRegister = MRI.createVirtualRegister(RC); 2090 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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/external/llvm/utils/TableGen/ |
H A D | AsmMatcherEmitter.cpp | 1171 const CodeGenRegisterClass &RC = **it; local 1173 Record *Def = RC.getDef(); 1176 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), 1177 RC.getOrder().end())]; 1179 CI->ClassName = RC.getName(); 1180 CI->Name = "MCK_" + RC.getName(); 1181 CI->ValueName = RC.getName(); 1183 CI->ValueName = CI->ValueName + "," + RC.getName();
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H A D | CodeGenRegisters.cpp | 789 // Returns true if RC is a strict subclass. 790 // RC is a sub-class of this class if it is a valid replacement for any 794 // 1. All RC registers are also in this. 795 // 2. The RC spill size must not be smaller than our spill size. 796 // 3. RC spill alignment must be compatible with ours. 857 CodeGenRegisterClass &RC = *RegClasses[rci - 1]; local 858 RC.SubClasses.resize(RegClasses.size()); 859 RC.SubClasses.set(RC.EnumValue); 861 // Normally, all subclasses have IDs >= rci, unless RC i 1040 addToMaps(CodeGenRegisterClass *RC) argument 1054 getOrCreateSubClass(const CodeGenRegisterClass *RC, const CodeGenRegister::Set *Members, StringRef Name) argument 1742 inferCommonSubClass(CodeGenRegisterClass *RC) argument 1780 inferSubClassWithSubReg(CodeGenRegisterClass *RC) argument 1823 inferMatchingSuperRegClass(CodeGenRegisterClass *RC, unsigned FirstSubRegRC) argument 1891 CodeGenRegisterClass *RC = RegClasses[rci]; local 1928 const CodeGenRegisterClass &RC = *RCs[i]; local [all...] |
/external/webrtc/src/modules/audio_coding/codecs/isac/main/source/ |
H A D | entropy_coding.c | 523 /* Find RC coefficients. */ 526 /* Quantize & code RC Coefficient. */ 529 /* RC -> AR coefficients */ 595 void WebRtcIsac_Rc2Poly(double* RC, int N, double* a) { argument 604 a[m] = RC[m - 1]; 606 a[k] += RC[m - 1] * tmp[m - k]; 613 void WebRtcIsac_Poly2Rc(double* a, int N, double* RC) { argument 618 RC[N - 1] = a[N]; 620 tmp_inv = 1.0 / (1.0 - RC[m] * RC[ [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 2183 const TargetRegisterClass *RC = *RCI; local 2187 if (!isLegalRC(RC)) 2190 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2194 std::make_pair(*I, RC); 2199 if (RC->hasType(VT))
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 243 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument 244 addRegisterClass(Ty, RC); 292 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument 293 addRegisterClass(Ty, RC); 2748 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 2775 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2781 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2813 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 2842 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2848 unsigned RD2 = RegInfo.createVirtualRegister(RC); 3189 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; local 3218 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 368 const TargetRegisterClass *RC = nullptr; local 374 RC = &X86::GR8RegClass; 378 RC = &X86::GR16RegClass; 382 RC = &X86::GR32RegClass; 387 RC = &X86::GR64RegClass; 392 RC = &X86::FR32RegClass; 395 RC = &X86::RFP32RegClass; 401 RC = &X86::FR64RegClass; 404 RC = &X86::RFP64RegClass; 412 ResultReg = createResultReg(RC); 594 const TargetRegisterClass *RC = nullptr; local 1501 const TargetRegisterClass *RC = nullptr; local 1585 const TargetRegisterClass *RC; member in struct:DivRemEntry 1744 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 1922 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 1991 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2019 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2193 const TargetRegisterClass *RC = nullptr; local 2332 const TargetRegisterClass *RC; local 2616 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local 3176 const TargetRegisterClass *RC = nullptr; local 3294 const TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); local 3308 const TargetRegisterClass *RC = nullptr; local [all...] |
H A D | X86ISelDAGToDAG.cpp | 2595 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); local 2597 Reg.getValueType(), Reg, RC), 0); 2631 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); local 2633 Reg.getValueType(), Reg, RC), 0);
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H A D | X86InstrInfo.cpp | 1867 const TargetRegisterClass *RC; local 1869 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; 1871 RC = Opc != X86::LEA32r ? 1884 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) 1918 NewSrc = MF.getRegInfo().createVirtualRegister(RC); 2986 const TargetRegisterClass *RC = local 2988 if (!RC) 2992 if (X86::GR16RegClass.hasSubClassEq(RC) || 2993 X86::GR32RegClass.hasSubClassEq(RC) || 2994 X86::GR64RegClass.hasSubClassEq(RC)) { 3179 getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load) argument 3266 getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument 3274 getLoadRegOpcode(unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument 3281 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 3299 storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 3320 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 3335 loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 4599 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); local 4721 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); local [all...] |
/external/pcre/dist/sljit/ |
H A D | sljitNativePPC_common.c | 128 #define RC(flags) ((flags & ALT_SET_FLAGS) >> 10) macro 535 /* This flag affects the RC() and OERC() macros. */
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/external/clang/include/clang/AST/ |
H A D | ASTContext.h | 560 void setRaw(const RawComment *RC) { argument 561 Data.setPointer(RC); 597 void addComment(const RawComment &RC) { argument 599 !SourceMgr.isInSystemHeader(RC.getSourceRange().getBegin())); 600 Comments.addComment(RC, BumpAlloc);
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 189 unsigned getReg(int RC, int RegNo); 1583 unsigned MipsAsmParser::getReg(int RC, int RegNo) { argument 1584 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
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