Searched defs:Reg (Results 101 - 125 of 253) sorted by relevance

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/external/llvm/include/llvm/MC/
H A DMCInst.h69 void setReg(unsigned Reg) { argument
71 RegVal = Reg;
111 static MCOperand CreateReg(unsigned Reg) { argument
114 Op.RegVal = Reg;
/external/llvm/lib/CodeGen/
H A DMachineCSE.cpp82 bool isPhysDefTriviallyDead(unsigned Reg,
95 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
122 unsigned Reg = MO.getReg(); local
123 if (!TargetRegisterInfo::isVirtualRegister(Reg))
125 if (!MRI->hasOneNonDBGUse(Reg))
129 MachineInstr *DefMI = MRI->getVRegDef(Reg);
151 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
167 MachineCSE::isPhysDefTriviallyDead(unsigned Reg, argument
183 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
187 if (!TRI->regsOverlap(MO.getReg(), Reg))
219 unsigned Reg = MO.getReg(); local
238 unsigned Reg = MO.getReg(); local
357 isProfitableToCSE(unsigned CSReg, unsigned Reg, MachineInstr *CSMI, MachineInstr *MI) argument
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H A DMachineSink.cpp90 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
95 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
147 MachineSinking::AllUsesDominatedByBlock(unsigned Reg, argument
152 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
156 if (MRI->use_nodbg_empty(Reg))
175 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
188 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
305 unsigned Reg = MO.getReg(); local
306 if (Reg == 0)
311 if (TargetRegisterInfo::isPhysicalRegister(Reg))
440 isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *SuccToSinkTo) argument
493 unsigned Reg = MO.getReg(); local
621 unsigned Reg = MO.getReg(); local
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H A DPHIElimination.cpp86 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
87 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
558 unsigned Reg = BBI->getOperand(i).getReg(); local
578 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges)
581 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
585 // If Reg is not live-in to MBB, it means it must be live-in to some
589 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
593 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges;
621 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) { argument
625 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MB
630 isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) argument
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H A DPrologEpilogInserter.cpp263 unsigned Reg = CSRegs[i]; local
265 if (F.getRegInfo().isPhysRegUsed(Reg) || F.getMMI().callsUnwindInit()) {
267 CSI.push_back(CalleeSavedInfo(Reg));
285 unsigned Reg = I->getReg(); local
286 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
289 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) {
298 FixedSlot->Reg != Reg)
354 unsigned Reg = CSI[i].getReg(); local
355 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
382 unsigned Reg = CSI[i].getReg(); local
791 unsigned Reg; local
872 unsigned Reg = MO.getReg(); local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp285 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) { argument
286 if (!LiveOutRegInfo.inBounds(Reg))
289 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
/external/llvm/lib/MC/MCParser/
H A DCOFFAsmParser.cpp581 unsigned Reg; local
582 if (ParseSEHRegisterNumber(Reg))
589 getStreamer().EmitWinCFIPushReg(Reg);
594 unsigned Reg; local
596 if (ParseSEHRegisterNumber(Reg))
613 getStreamer().EmitWinCFISetFrame(Reg, Off);
635 unsigned Reg; local
637 if (ParseSEHRegisterNumber(Reg))
655 getStreamer().EmitWinCFISaveReg(Reg, Off);
662 unsigned Reg; local
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/external/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp491 for (auto Reg : Ord) {
492 if (!AvailableRegs[Reg])
494 if ((C == Color::Even && (Reg % 2) == 0) ||
495 (C == Color::Odd && (Reg % 2) == 1))
496 return Reg;
510 int Reg = scavengeRegister(G, C, MBB); local
511 if (Reg == -1) {
515 DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n");
555 Substs[MO.getReg()] = Reg;
556 MO.setReg(Reg);
688 getColor(unsigned Reg) argument
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H A DAArch64AsmPrinter.cpp216 unsigned Reg = MO.getReg(); local
217 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
219 O << AArch64InstPrinter::getRegisterName(Reg);
232 unsigned Reg = MO.getReg(); local
237 Reg = getWRegFromXReg(Reg);
240 Reg = getXRegFromWReg(Reg);
244 O << AArch64InstPrinter::getRegisterName(Reg);
257 unsigned Reg local
287 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR; local
329 unsigned Reg = MO.getReg(); local
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H A DAArch64ConditionalCompares.cpp223 unsigned Reg = I.getOperand(oi).getReg(); local
225 assert((!HeadReg || HeadReg == Reg) && "Inconsistent PHI operands");
226 HeadReg = Reg;
229 assert((!CmpBBReg || CmpBBReg == Reg) && "Inconsistent PHI operands");
230 CmpBBReg = Reg;
247 // PHI operands are (Reg, MBB) at (oi-2, oi-1).
H A DAArch64LoadStoreOptimizer.cpp349 unsigned Reg = MO.getReg(); local
351 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
354 assert(MO.isUse() && "Reg operand not a def and not a use?!?");
355 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
395 unsigned Reg = FirstMI->getOperand(0).getReg(); local
465 if (MayLoad && Reg == MI->getOperand(0).getReg()) {
/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp67 unsigned Reg, unsigned Lane,
114 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
137 unsigned Reg = MO.getReg(); local
139 if (TargetRegisterInfo::isVirtualRegister(Reg))
140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
142 return TRC->contains(Reg);
196 unsigned Reg = MO.getReg(); local
197 if (!TRI->isVirtualRegister(Reg))
199 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
225 II = MRI->use_instr_begin(Reg), E
377 unsigned Reg = MI->getOperand(I).getReg(); local
425 createDupLane(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg, unsigned Lane, bool QPR) argument
528 optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) argument
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H A DARMMachineFunctionInfo.h210 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
H A DMLxExpansionPass.cpp66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
90 unsigned Reg = MI->getOperand(1).getReg(); local
91 if (TargetRegisterInfo::isPhysicalRegister(Reg))
95 MachineInstr *DefMI = MRI->getVRegDef(Reg);
100 Reg = DefMI->getOperand(1).getReg();
101 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
102 DefMI = MRI->getVRegDef(Reg);
106 Reg = DefMI->getOperand(2).getReg();
107 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
108 DefMI = MRI->getVRegDef(Reg);
118 unsigned Reg = MI->getOperand(0).getReg(); local
144 unsigned Reg = MI->getOperand(1).getReg(); local
185 hasRAWHazard(unsigned Reg, MachineInstr *MI) const argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp204 static bool isEvenReg(unsigned Reg) { argument
205 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
206 Hexagon::IntRegsRegClass.contains(Reg));
207 return (Reg - Hexagon::R0) % 2 == 0;
374 unsigned Reg = Op.getReg(); local
375 MachineInstr *DefInst = LastDef[Reg];
402 unsigned Reg = Op.getReg(); local
403 if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
404 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
407 } else if (Hexagon::IntRegsRegClass.contains(Reg))
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H A DHexagonNewValueJump.cpp153 unsigned Reg = II->getOperand(i).getReg(); local
158 if (localBegin->modifiesRegister(Reg, TRI) ||
159 localBegin->readsRegister(Reg, TRI))
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp181 unsigned Reg = CSI[e-i-1].getReg(); local
182 switch (Reg) {
186 MIB.addReg(Reg, Flags);
328 int Reg =0; local
378 Reg = Available.find_first();
380 if (Reg == -1) {
381 Reg = Candidates.find_first();
382 Candidates.reset(Reg);
383 if (DefReg != Reg) {
384 FirstRegSaved = Reg;
463 validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount) argument
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H A DMipsFastISel.cpp26 unsigned Reg; member in union:__anon26050::Address::__anon26052
33 Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
151 Addr.Base.Reg = getRegForValue(Obj);
152 return Addr.Base.Reg != 0;
190 EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
239 EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
H A DMipsSEFrameLowering.cpp324 unsigned Reg = I->getReg(); local
326 // If Reg is a double precision register, emit two cfa_offsets,
328 if (Mips::AFGR64RegClass.contains(Reg)) {
330 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
332 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
347 // Reg is either in GPR32 or FGR32.
349 nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
371 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true); local
373 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
463 unsigned Reg local
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/external/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.h172 void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); } argument
/external/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.cpp196 unsigned Reg, bool UnfoldLoad,
294 unsigned Reg = LI->first; local
295 if (TargetRegisterInfo::isVirtualRegister(Reg) ||
296 !IndirectRC->contains(Reg))
303 if (IndirectRC->getRegister(RegIndex) == Reg)
195 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
/external/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp122 unsigned Reg = IntRegDecoderTable[RegNo]; local
123 Inst.addOperand(MCOperand::CreateReg(Reg));
133 unsigned Reg = IntRegDecoderTable[RegNo]; local
134 Inst.addOperand(MCOperand::CreateReg(Reg));
145 unsigned Reg = FPRegDecoderTable[RegNo]; local
146 Inst.addOperand(MCOperand::CreateReg(Reg));
157 unsigned Reg = DFPRegDecoderTable[RegNo]; local
158 Inst.addOperand(MCOperand::CreateReg(Reg));
170 unsigned Reg = QFPRegDecoderTable[RegNo]; local
171 if (Reg
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/external/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp77 Reference getRegReferences(MachineInstr *MI, unsigned Reg);
108 // SubReg of Reg.
109 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) { argument
113 MI->getOperand(0).getReg() == Reg &&
130 if (MI->getOperand(1).getReg() == Reg &&
138 // Describe the references to Reg in MI, including sub- and super-registers.
139 Reference SystemZElimCompare::getRegReferences(MachineInstr *MI, unsigned Reg) { argument
145 if (MOReg == Reg || TRI->regsOverlap(MOReg, Reg)) {
148 Ref.IndirectUse |= (MOReg != Reg);
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/external/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp208 unsigned Reg = MO.getReg(); local
213 Reg = getX86SubSuperRegister(Reg, VT);
215 O << X86ATTInstPrinter::getRegisterName(Reg);
350 unsigned Reg = MO.getReg(); local
354 Reg = getX86SubSuperRegister(Reg, MVT::i8);
357 Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
360 Reg
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/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp219 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); local
220 Inst.addOperand(MCOperand::CreateReg(Reg));
231 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); local
232 Inst.addOperand(MCOperand::CreateReg(Reg));

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