/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.h | 96 DebugLoc dl; member in class:llvm::SelectionDAGBuilder::DanglingDebugInfo 99 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { } 101 DI(di), dl(DL), SDNodeOrder(SDNO) { } 103 DebugLoc getdl() { return dl; }
|
H A D | LegalizeIntegerTypes.cpp | 241 SDLoc dl(N); 249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 253 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 260 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 274 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 278 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 285 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); 288 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 296 SDLoc dl(N); 299 return DAG.getNode(ISD::SRL, dl, NV 2515 IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc dl) argument [all...] |
H A D | TargetLowering.cpp | 89 bool isSigned, SDLoc dl, 107 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) 120 SDLoc dl) const { 202 dl).first; 206 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, 210 dl).first; 211 NewLHS = DAG.getNode(ISD::SETCC, dl, 214 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); 284 SDLoc dl(Op); 302 SDValue New = DAG.getNode(Op.getOpcode(), dl, V 86 makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn, bool isReturnValueUsed) const argument 321 ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, SDLoc dl) argument 2617 BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const argument [all...] |
H A D | SelectionDAG.cpp | 1479 SDValue SelectionDAG::getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, argument 1593 new (NodeAllocator) ShuffleVectorSDNode(VT, dl.getIROrder(), 1594 dl.getDebugLoc(), N1, N2, 1601 SDValue SelectionDAG::getConvertRndSat(EVT VT, SDLoc dl, argument 1618 CvtRndSatSDNode *N = new (NodeAllocator) CvtRndSatSDNode(VT, dl.getIROrder(), 1619 dl.getDebugLoc(), 1654 SDValue SelectionDAG::getEHLabel(SDLoc dl, SDValue Root, MCSymbol *Label) { argument 1663 SDNode *N = new (NodeAllocator) EHLabelSDNode(dl.getIROrder(), 1664 dl.getDebugLoc(), Root, Label); 1728 SDValue SelectionDAG::getAddrSpaceCast(SDLoc dl, EV argument 1790 FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl) argument 3681 getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG, SDLoc dl) argument 3708 getMemsetStringVal(EVT VT, SDLoc dl, SelectionDAG &DAG, const TargetLowering &TLI, StringRef Str) argument 3750 getMemBasePlusOffset(SDValue Base, unsigned Offset, SDLoc dl, SelectionDAG &DAG) argument 3883 getMemcpyLoadsAndStores(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) argument 4000 getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) argument 4097 getMemsetStores(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool isVol, MachinePointerInfo DstPtrInfo) argument 4180 getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) argument 4248 getMemmove(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) argument 4304 getMemset(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, MachinePointerInfo DstPtrInfo) argument 4368 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList, ArrayRef<SDValue> Ops, MachineMemOperand *MMO, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) argument 4403 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList, ArrayRef<SDValue> Ops, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 4412 getAtomicCmpSwap( unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) argument 4439 getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) argument 4455 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value* PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 4486 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 4514 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 4528 getMergeValues(ArrayRef<SDValue> Ops, SDLoc dl) argument 4540 getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef<SDValue> Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol, bool ReadMem, bool WriteMem) argument 4563 getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef<SDValue> Ops, EVT MemVT, MachineMemOperand *MMO) argument 4635 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo, const MDNode *Ranges) argument 4668 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO) argument 4716 getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo, const MDNode *Ranges) argument 4729 getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO) argument 4737 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo) argument 4749 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) argument 4758 getIndexedLoad(SDValue OrigLoad, SDLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) argument 4769 getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo) argument 4796 getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachineMemOperand *MMO) argument 4823 getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT,bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo) argument 4850 getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, EVT SVT, MachineMemOperand *MMO) argument 4893 getIndexedStore(SDValue OrigStore, SDLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) argument 4919 getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align) argument 5553 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT) argument 5559 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1) argument 5566 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument 5574 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5582 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, ArrayRef<SDValue> Ops) argument 5589 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2) argument 5595 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1) argument 5603 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5611 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5620 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, ArrayRef<SDValue> Ops) argument 5628 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument 5637 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 5646 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef<SDValue> Ops) argument 5654 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, EVT VT4, ArrayRef<SDValue> Ops) argument 5662 getMachineNode(unsigned Opcode, SDLoc dl, ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops) argument 6206 AddrSpaceCastSDNode(unsigned Order, DebugLoc dl, EVT VT, SDValue X, unsigned SrcAS, unsigned DestAS) argument 6212 MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, EVT memvt, MachineMemOperand *mmo) argument 6223 MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, ArrayRef<SDValue> Ops, EVT memvt, MachineMemOperand *mmo) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 115 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 122 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes, 125 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes, 130 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 135 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, 177 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); local 194 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, 199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 206 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize), 211 BuildMI(MBB, MBBI, dl, TI 114 emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument 129 emitSPUpdate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument 574 DebugLoc dl = MBBI->getDebugLoc(); local 1637 DebugLoc dl = Old->getDebugLoc(); local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 102 DebugLoc dl, unsigned Base, unsigned WordOffset, 107 DebugLoc dl, 122 DebugLoc dl, 334 DebugLoc dl, unsigned Base, 386 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base)) 404 AddDefaultT1CC(BuildMI(MBB, --MBBI, dl, TII->get(ARM::tSUBi8), Base)) 417 unsigned PredReg, unsigned Scratch, DebugLoc dl, 479 BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase) 483 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)) 487 BuildMI(MBB, MBBI, dl, TI 332 UpdateBaseRegUses(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc dl, unsigned Base, unsigned WordOffset, ARMCC::CondCodes Pred, unsigned PredReg) argument 413 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument 610 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument 718 DebugLoc dl = Loc->getDebugLoc(); local 997 DebugLoc dl = MI->getDebugLoc(); local 1135 DebugLoc dl = MI->getDebugLoc(); local 1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1452 DebugLoc dl = MBBI->getDebugLoc(); local 1875 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument 2042 DebugLoc dl; local [all...] |
H A D | ARMBaseInstrInfo.cpp | 1841 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 1846 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) 1868 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 1840 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
|
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 94 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl); 95 SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl); 97 SDLoc dl); 99 SDLoc dl); 100 SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl); 101 SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl); 387 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) { argument 402 CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0); 404 dl, PointerTy, 415 SDNode* Result = CurDAG->getMachineNode(Opcode, dl, 433 SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode, SDLoc dl) argument 500 SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode, SDLoc dl) argument 580 SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) argument 692 SelectIndexedStore(StoreSDNode *ST, SDLoc dl) argument 762 SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl) argument [all...] |
H A D | HexagonISelLowering.cpp | 302 SDLoc dl) { 305 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 319 SDLoc dl, SelectionDAG &DAG) const { 338 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 351 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); 367 SDLoc dl, SelectionDAG &DAG, 382 Chain = DAG.getCopyFromReg(Chain, dl, 398 SDLoc &dl = CLI.DL; local 415 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32); 469 DAG.getCopyFromReg(Chain, dl, QR 300 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) argument 315 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument 363 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const argument 828 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 121 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); 237 DebugLoc dl; local 243 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 244 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 246 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 260 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 275 DebugLoc dl; local 279 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); 280 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 283 BuildMI(FirstMBB, MBBI, dl, TI 492 SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl) argument [all...] |
H A D | PPCInstrInfo.cpp | 625 MachineBasicBlock::iterator MI, DebugLoc dl, 680 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) 684 BuildMI(MBB, MI, dl, get(OpCode), DestReg) 624 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, unsigned DestReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 260 SDLoc dl(GA); 263 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); 268 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); 270 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); 332 SDLoc dl(CP); 342 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); 355 SDLoc dl(Op); 364 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); 367 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 369 return DAG.getNode(XCoreISD::BR_JT32, dl, MV 1035 SDLoc &dl = CLI.DL; local 1063 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument 1110 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1248 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1272 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1455 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument 1545 DebugLoc dl = MI->getDebugLoc(); local [all...] |
/external/qemu-pc-bios/vgabios/ |
H A D | vgabios.c | 2889 mov dl, al variable 2896 cmp dl, #0x01 variable 2899 cmp dl, #0x02 variable 2902 mov al, dl 2962 mov dl, al variable 2963 and dl, #0x01 variable 2964 shl dl, 3 variable 2970 or al, dl 3002 mov dl, al variable 3003 and dl, # variable 3004 xor dl, #0x01 variable 3005 shl dl, 1 variable 3024 mov dl, al variable 3025 and dl, #0x01 variable 3026 xor dl, #0x01 variable 3847 mov dl, #0x00 local 3852 mov dl, #0x00 local 3863 mov dl, #0x10 ;; I/O space #0 local 3888 add dl, #4 local [all...] |
/external/wpa_supplicant_8/hs20/client/ |
H A D | osu_client.c | 840 char *type, *dl = NULL, *ul = NULL; local 867 dl = xml_node_get_text(ctx->xml, node); 873 if (dl == NULL && ul == NULL) { 878 if (dl) 880 dl); 886 if (dl && 887 set_cred(ctx->ifname, id, "min_dl_bandwidth_home", dl) < 0) 893 if (dl && 894 set_cred(ctx->ifname, id, "min_dl_bandwidth_roaming", dl) < 903 xml_node_get_text_free(ctx->xml, dl); [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 486 SDLoc dl(Op); 488 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); 489 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op); 654 SDLoc dl = CLI.DL; local 676 dl); 710 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, 720 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); 727 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, 748 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, 764 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MV 1626 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1934 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 343 SDLoc dl, 368 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 380 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 390 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 396 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 399 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 400 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 406 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 408 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 410 Arg = DAG.getNode(ISD::AssertSext, dl, MV 339 LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 686 SDLoc &dl = CLI.DL; local 2904 DebugLoc dl = MI->getDebugLoc(); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 538 SDLoc dl(N); 541 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl, 545 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, 974 SDLoc dl(N); 1186 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 1717 SDLoc dl, 1757 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT, 1769 SDLoc dl(Node); 1800 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val); 1846 dl, NV 1716 getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG, SDLoc dl, enum AtomicOpc &Op, MVT NVT, SDValue Val) argument [all...] |
H A D | X86ISelLowering.cpp | 73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, 77 SelectionDAG &DAG, SDLoc dl, 101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, 106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 119 SelectionDAG &DAG, SDLoc dl) { 122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128); 127 SelectionDAG &DAG, SDLoc dl) { 129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256); 134 SDLoc dl, unsigned vectorWidth) { 153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultV 76 ExtractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl, unsigned vectorWidth) argument 118 Extract128BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl) argument 126 Extract256BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl) argument 132 InsertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl, unsigned vectorWidth) argument 162 Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl) argument 169 Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl) argument 180 Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl) argument 187 Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl) argument 1865 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument 2036 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2144 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) argument 2187 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument 2228 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2515 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 2550 EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, unsigned SlotSize, int FPDiff, SDLoc dl) argument 2571 SDLoc &dl = CLI.DL; local 3389 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SelectionDAG &DAG) argument 3400 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, unsigned TargetMask, SelectionDAG &DAG) argument 3414 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) argument 3427 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG) argument 4891 getZeroVector(EVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG, SDLoc dl) argument 4938 getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG, SDLoc dl) argument 4972 getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, SDValue V2) argument 4983 getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 4995 getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 5553 getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, SDLoc dl) argument 5567 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) argument [all...] |
/external/opencv/cv/src/ |
H A D | cvhaar.cpp | 1547 int dl = 0; local 1553 sscanf( stage, "%d%n", &count, &dl ); 1554 stage += dl; 1567 sscanf( stage, "%d%n", &classifier->count, &dl ); 1568 stage += dl; 1583 sscanf( stage, "%d%n", &rects, &dl ); 1584 stage += dl; 1594 &(classifier->haar_feature[l].rect[k].weight), &dl ); 1595 stage += dl; 1598 sscanf( stage, "%s%n", str, &dl ); [all...] |
/external/chromium_org/third_party/icu/source/i18n/ |
H A D | decimfmt.cpp | 1069 DigitList *dl = number.getDigitList(); local 1070 if (dl != NULL) { 1071 DigitList clonedDL(*dl); 2207 // TODO: set the dl to infinity, and let it fall into the code below.
|
/external/chromium_org/third_party/icu/source/test/intltest/ |
H A D | numfmtst.cpp | 490 /*static void setFromString(DigitList& dl, const char* str) { 493 dl.clear(); 496 dl.fIsPositive = FALSE; 498 dl.fIsPositive = TRUE; 500 dl.fDecimalAt = dl.fCount; 503 dl.append(c); 507 dl.fDecimalAt = dl.fCount; 534 DigitList dl; 6433 DigitList dl; local [all...] |
/external/clang/lib/CodeGen/ |
H A D | TargetInfo.cpp | 5681 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl) argument 5682 : Context(c), DL(dl), Size(0), InReg(false) {}
|
/external/icu/icu4c/source/test/intltest/ |
H A D | numfmtst.cpp | 494 /*static void setFromString(DigitList& dl, const char* str) { 497 dl.clear(); 500 dl.fIsPositive = FALSE; 502 dl.fIsPositive = TRUE; 504 dl.fDecimalAt = dl.fCount; 507 dl.append(c); 511 dl.fDecimalAt = dl.fCount; 538 DigitList dl; 6462 DigitList dl; local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 467 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } argument 741 SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs, 748 debugLoc(dl), IROrder(Order) { 758 SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs) 761 UseList(nullptr), NumOperands(0), NumValues(VTs.NumVTs), debugLoc(dl), 946 UnarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, argument 948 : SDNode(Opc, Order, dl, VTs) { 958 BinarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, argument 960 : SDNode(Opc, Order, dl, VT 971 BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y) argument 1000 TernarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y, SDValue Z) argument 1190 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 1198 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 1207 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 1216 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, const SDValue* AllOps, SDUse *DynOps, unsigned NumOps, MachineMemOperand *MMO, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) argument 1272 MemIntrinsicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, ArrayRef<SDValue> Ops, EVT MemoryVT, MachineMemOperand *MMO) argument 1305 ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, SDValue N1, SDValue N2, const int *M) argument 1707 EHLabelSDNode(unsigned Order, DebugLoc dl, SDValue ch, MCSymbol *L) argument 1760 CvtRndSatSDNode(EVT VT, unsigned Order, DebugLoc dl, ArrayRef<SDValue> Ops, ISD::CvtCode Code) argument 1803 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, DebugLoc dl, SDValue *Operands, unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument 1841 LoadSDNode(SDValue *ChainPtrOff, unsigned Order, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument 1870 StoreSDNode(SDValue *ChainValuePtrOff, unsigned Order, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument [all...] |
/external/valgrind/main/VEX/priv/ |
H A D | host_s390_defs.c | 2037 s390_disasm(ENC3(MNM, GPR, SDXB), "dl", r1, dh2, dl2, x2, b2); 4925 s390_emit_MFYw(UChar *p, UChar r1, UChar x, UChar b, UShort dl, UChar dh) argument 4928 return s390_emit_MFY(p, r1, x, b, dl, dh); 4932 p = s390_emit_LY(p, R0, x, b, dl, dh); 4938 s390_emit_MHYw(UChar *p, UChar r1, UChar x, UChar b, UShort dl, UChar dh) argument 4941 return s390_emit_MHY(p, r1, x, b, dl, dh); 4945 p = s390_emit_LHY(p, R0, x, b, dl, dh); 5164 s390_emit_LLCw(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl, UChar dh) argument 5167 return s390_emit_LLC(p, r1, x2, b2, dl, dh); 5171 p = s390_emit_IC(p, r1, x2, b2, dl); 5182 s390_emit_LLHw(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl, UChar dh) argument 5249 s390_emit_LTw(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl, UChar dh) argument 5265 s390_emit_LTGw(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl, UChar dh) argument [all...] |