/external/lldb/source/Plugins/Process/Utility/ |
H A D | RegisterContextDummy.cpp | 78 RegisterContextDummy::GetRegisterInfoAtIndex (size_t reg) argument 80 if (reg)
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H A D | RegisterContextMacOSXFrameBackchain.cpp | 62 RegisterContextMacOSXFrameBackchain::GetRegisterInfoAtIndex (size_t reg) argument 64 return m_thread.GetRegisterContext()->GetRegisterInfoAtIndex(reg);
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/external/ltrace/sysdeps/linux-gnu/arm/ |
H A D | regs.c | 43 arm_get_register(struct process *proc, enum arm_register reg, uint32_t *lp) argument 46 long l = ptrace(PTRACE_PEEKUSER, proc->pid, (void *)(reg * 4L), 0); 54 arm_set_register(struct process *proc, enum arm_register reg, uint32_t lp) argument 57 (void *)(reg * 4L), (void *)lp); 61 arm_get_register_offpc(struct process *proc, enum arm_register reg, argument 64 if (arm_get_register(proc, reg, lp) < 0) 66 if (reg == ARM_REG_PC) 126 uint32_t reg; local 127 if (arm_get_register(proc, r, ®) < 0) 131 return (arch_addr_t)(uintptr_t)reg; [all...] |
/external/mesa3d/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_util.c | 53 const struct tgsi_src_register *reg, 58 return reg->SwizzleX; 60 return reg->SwizzleY; 62 return reg->SwizzleZ; 64 return reg->SwizzleW; 74 const struct tgsi_full_src_register *reg, 78 ®->Register, 84 struct tgsi_src_register *reg, 90 reg->SwizzleX = swizzle; 93 reg 52 tgsi_util_get_src_register_swizzle( const struct tgsi_src_register *reg, unsigned component ) argument 73 tgsi_util_get_full_src_register_swizzle( const struct tgsi_full_src_register *reg, unsigned component ) argument 83 tgsi_util_set_src_register_swizzle( struct tgsi_src_register *reg, unsigned swizzle, unsigned component ) argument 107 tgsi_util_get_full_src_register_sign_mode( const struct tgsi_full_src_register *reg, unsigned component ) argument 136 tgsi_util_set_full_src_register_sign_mode( struct tgsi_full_src_register *reg, unsigned sign_mode ) argument [all...] |
/external/mesa3d/src/gallium/drivers/r300/ |
H A D | r300_vs.c | 110 int i, reg = 0; local 120 c->code->outputs[outputs->pos] = reg++; 127 c->code->outputs[outputs->psize] = reg++; 133 * pretend it does by skipping output index reg so the colors 140 c->code->outputs[outputs->color[i]] = reg++; 143 reg++; 150 c->code->outputs[outputs->bcolor[i]] = reg++; 152 reg++; 159 c->code->outputs[outputs->generic[i]] = reg++; 165 c->code->outputs[outputs->fog] = reg [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUAsmPrinter.cpp | 74 unsigned reg; local 79 reg = MO.getReg(); 80 if (reg == AMDGPU::VCC) { 84 if (reg == AMDGPU::EXEC) { 87 if (AMDGPU::SReg_32RegClass.contains(reg)) { 90 } else if (AMDGPU::VReg_32RegClass.contains(reg)) { 93 } else if (AMDGPU::SReg_64RegClass.contains(reg)) { 96 } else if (AMDGPU::VReg_64RegClass.contains(reg)) { 99 } else if (AMDGPU::SReg_128RegClass.contains(reg)) { 102 } else if (AMDGPU::VReg_128RegClass.contains(reg)) { [all...] |
/external/mesa3d/src/gallium/drivers/svga/ |
H A D | svga_tgsi_decl_sm30.c | 95 * For example, if usage = SVGA3D_DECLUSAGE_TEXCOORD, reg.num = 1, and 100 SVGA3dShaderDestToken reg, 115 dcl.dst = reg; 132 SVGA3dShaderDestToken reg = local 135 if (!emit_decl( emit, reg, 0, 0 )) 152 struct src_register reg; local 162 reg = src_register( SVGA3DREG_INPUT, 165 *out = emit->ps_depth_fog = reg; 169 return emit_decl( emit, dst( reg ), SVGA3D_DECLUSAGE_TEXCOORD, 0 ); 183 SVGA3dShaderDestToken reg; local 99 emit_decl(struct svga_shader_emitter *emit, SVGA3dShaderDestToken reg, unsigned usage, unsigned index) argument 402 SVGA3dShaderDestToken reg; local [all...] |
/external/mesa3d/src/mesa/drivers/dri/i915/ |
H A D | i915_debug_fp.c | 165 print_reg_neg_swizzle(GLuint reg) argument 169 if ((reg & REG_SWIZZLE_MASK) == REG_SWIZZLE_XYZW && 170 (reg & REG_NEGATE_MASK) == 0) 176 if (reg & (1 << ((i * 4) + 3))) 179 switch ((reg >> (i * 4)) & 0x7) {
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_curbe.c | 103 GLuint reg = 0; local 107 reg = 0; 108 brw->curbe.wm_start = reg; 109 brw->curbe.wm_size = nr_fp_regs; reg += nr_fp_regs; 110 brw->curbe.clip_start = reg; 111 brw->curbe.clip_size = nr_clip_regs; reg += nr_clip_regs; 112 brw->curbe.vs_start = reg; 113 brw->curbe.vs_size = nr_vp_regs; reg += nr_vp_regs; 114 brw->curbe.total_size = reg;
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H A D | brw_fs_live_variables.cpp | 68 int reg = inst->src[i].reg; local 70 if (!bd[b].def[reg]) 71 bd[b].use[reg] = true; 80 inst->regs_written() == v->virtual_grf_sizes[inst->dst.reg] && 84 int reg = inst->dst.reg; local 85 if (!bd[b].use[reg]) 86 bd[b].def[reg] = true; 190 int reg local 197 int reg = inst->dst.reg; local [all...] |
H A D | brw_gs.h | 99 } reg; member in struct:brw_gs_compile
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H A D | brw_wm_pass2.c | 49 GLuint reg) 55 c->pass2_grf[reg].value = value; 56 c->pass2_grf[reg].nextuse = 0; 58 value->resident = &c->pass2_grf[reg]; 59 value->hw_reg = brw_vec8_grf(reg*2, 0); 175 * value is calculated, so we can just take this reg without any 188 * TODO: implement spill-to-reg so that we can rearrange discontigous 198 GLuint reg = 0; local 213 reg = i; 222 if (grf[reg 47 prealloc_reg(struct brw_wm_compile *c, struct brw_wm_value *value, GLuint reg) argument 234 GLuint reg = search_contiguous_regs(c, nr, thisinsn); local 278 GLuint reg = search_contiguous_regs(c, 1, thisinsn); local [all...] |
/external/openfst/src/include/fst/ |
H A D | generic-register.h | 152 RegisterType *reg = RegisterType::GetRegister(); local 153 reg->SetEntry(key, entry);
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/external/openfst/src/include/fst/script/ |
H A D | script-impl.h | 184 typename OpReg::Register *reg = OpReg::Register::GetRegister(); local 186 typename OpReg::OpType op = reg->GetOperation(op_name, arc_type);
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/external/valgrind/main/VEX/priv/ |
H A D | guest_generic_x87.h | 82 UChar reg[80]; member in struct:__anon31594 102 UChar reg[80]; member in struct:__anon31595
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/external/valgrind/main/none/tests/x86/ |
H A D | bt_everything.c | 148 UInt reg; local 185 reg = 0; 192 case 0: c = btsl_reg(reg, bitoff, ®); break; 193 case 1: c = btrl_reg(reg, bitoff, ®); break; 194 case 2: c = btcl_reg(reg, bitoff, ®); break; 195 case 3: c = btl_reg(reg, bitoff, ®); brea [all...] |
/external/bluetooth/bluedroid/bta/sys/ |
H A D | bta_sys_int.h | 59 tBTA_SYS_REG *reg[BTA_ID_MAX]; /* registration structures */ member in struct:__anon983
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/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_tgsi.c | 288 const struct tgsi_full_src_register *reg = &inst->Src[src_op]; local 296 swizzle = tgsi_util_get_full_src_register_swizzle(reg, chan_index); 303 assert(reg->Register.Index <= bld_base->info->file_max[reg->Register.File]); 305 if (bld_base->emit_fetch_funcs[reg->Register.File]) { 306 res = bld_base->emit_fetch_funcs[reg->Register.File](bld_base, reg, stype, 313 if (reg->Register.Absolute) { 317 if (reg->Register.Negate) { 327 reg [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
H A D | i915_debug_fp.c | 180 print_reg_neg_swizzle(struct debug_stream *stream, unsigned reg) argument 184 if ((reg & REG_SWIZZLE_MASK) == REG_SWIZZLE_XYZW && 185 (reg & REG_NEGATE_MASK) == 0) 191 if (reg & (1 << ((i * 4) + 3))) 194 switch ((reg >> (i * 4)) & 0x7) {
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
H A D | r300_fragprog_swizzle.c | 107 static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) argument 117 if (reg.Abs || reg.Negate) 121 unsigned int swz = GET_SWZ(reg.Swizzle, j); 134 if (GET_SWZ(reg.Swizzle, j) != RC_SWIZZLE_UNUSED) 137 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant)) 140 sd = lookup_native_swizzle(reg.Swizzle); 141 if (!sd || (reg.File == RC_FILE_PRESUB && sd->srcp_stride == 0))
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H A D | radeon_program_tex.c | 38 struct rc_src_register reg = { 0, 0, 0, 0, 0, 0 }; local 40 reg.File = RC_FILE_NONE; 41 reg.Swizzle = combine_swizzles(RC_SWIZZLE_0000, 43 return reg; 49 struct rc_src_register reg = { 0, 0, 0, 0, 0, 0 }; local 51 reg.File = RC_FILE_NONE; 52 reg.Swizzle = combine_swizzles(RC_SWIZZLE_1111, 54 return reg;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/ |
H A D | r300_vs_draw.c | 78 static void emit_temp(struct tgsi_transform_context *ctx, unsigned reg) argument 84 decl.Range.First = decl.Range.Last = reg; 90 unsigned reg) 101 decl.Range.First = decl.Range.Last = reg; 88 emit_output(struct tgsi_transform_context *ctx, unsigned name, unsigned index, unsigned interp, unsigned reg) argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/ |
H A D | radeonsi_pm4.c | 56 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val) argument 60 if (reg >= SI_CONFIG_REG_OFFSET && reg <= SI_CONFIG_REG_END) { 62 reg -= SI_CONFIG_REG_OFFSET; 64 } else if (reg >= SI_SH_REG_OFFSET && reg <= SI_SH_REG_END) { 66 reg -= SI_SH_REG_OFFSET; 68 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg <= SI_CONTEXT_REG_END) { 70 reg 109 si_pm4_sh_data_end(struct si_pm4_state *state, unsigned reg) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/state_trackers/clover/api/ |
H A D | memory.cpp | 71 const cl_buffer_region *reg = (const cl_buffer_region *)op_info; local 73 if (!reg || 74 reg->origin > parent->size() || 75 reg->origin + reg->size > parent->size()) 78 if (!reg->size) 82 return new sub_buffer(*parent, flags, reg->origin, reg->size);
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/ |
H A D | i915_program.h | 75 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20)) 78 #define GET_UREG_TYPE(reg) (((reg)>>UREG_TYPE_SHIFT)®_TYPE_MASK) 79 #define GET_UREG_NR(reg) (((reg)>>UREG_NR_SHIFT)®_NR_MASK) 88 swizzle(int reg, int x, int y, int z, int w) argument 90 return ((reg & ~UREG_XYZW_CHANNEL_MASK) | 91 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) | 92 CHANNEL_SRC(GET_CHANNEL_SRC(reg, 100 negate(int reg, int x, int y, int z, int w) argument [all...] |