Searched refs:MRI (Results 101 - 125 of 247) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DMachineSSAUpdater.h55 MachineRegisterInfo *MRI; member in class:llvm::MachineSSAUpdater
H A DRegisterPressure.h44 const MachineRegisterInfo *MRI);
51 const MachineRegisterInfo *MRI);
152 const MachineRegisterInfo *MRI);
254 const MachineRegisterInfo *MRI;
/external/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.h36 MachineRegisterInfo &MRI; member in class:llvm::CriticalAntiDepBreaker
H A DUnreachableBlockElim.cpp196 MachineRegisterInfo &MRI = F.getRegInfo(); local
197 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
198 MRI.replaceRegWith(Output, Input);
H A DInlineSpiller.cpp68 MachineRegisterInfo &MRI; member in class:__anon25751::InlineSpiller
153 MRI(mf.getRegInfo()),
244 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
245 E = MRI.reg_instr_nodbg_end(); RI != E; ) {
284 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
745 MRI.getRegClass(SVI.SpillReg), &TRI);
780 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
943 RI = MRI
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H A DLiveIntervalAnalysis.cpp112 MRI = &MF->getRegInfo();
123 VirtRegIntervals.resize(MRI->getNumVirtRegs());
149 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
193 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
195 if (MRI->reg_nodbg_empty(Reg))
249 if (!MRI->reg_empty(*Supers))
260 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
332 I = MRI->reg_instr_begin(li->reg), E = MRI
726 const MachineRegisterInfo& MRI; member in class:LiveIntervals::HMEditor
734 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, const TargetRegisterInfo& TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags) argument
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H A DLiveRangeCalc.cpp27 MRI = &MF->getRegInfo();
41 assert(MRI && Indexes && "call reset() first");
45 for (MachineOperand &MO : MRI->def_operands(Reg)) {
64 assert(MRI && Indexes && "call reset() first");
67 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
H A DRegisterCoalescer.cpp80 MachineRegisterInfo* MRI; member in class:__anon25794::RegisterCoalescer
271 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local
283 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
285 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
290 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
291 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
624 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
647 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
668 for (MachineRegisterInfo::use_iterator UI = MRI
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H A DTwoAddressInstructionPass.cpp75 MachineRegisterInfo *MRI; member in class:__anon25830::TwoAddressInstructionPass
231 UI = MRI->use_nodbg_begin(SavedReg),
232 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
319 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
402 const MachineRegisterInfo *MRI,
410 (allowFalsePositives || MRI->hasOneUse(Reg)))
416 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
419 if (std::next(Begin) != MRI->def_end())
452 MachineRegisterInfo *MRI,
456 if (!MRI
401 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument
451 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument
[all...]
H A DLiveRegMatrix.cpp52 MRI = &MF.getRegInfo();
80 MRI->setPhysRegUsed(PhysReg);
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp57 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, argument
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp396 const MCRegisterInfo &MRI,
404 const MCRegisterInfo &MRI,
412 const MCRegisterInfo &MRI,
420 const MCRegisterInfo &MRI,
395 createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
403 createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
411 createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
419 createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
H A DMipsMCTargetDesc.cpp78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument
81 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
104 const MCRegisterInfo &MRI,
106 return new MipsInstPrinter(MAI, MII, MRI);
100 createMipsMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.h28 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp69 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument
83 MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
192 const MCRegisterInfo &MRI,
195 return new PPCInstPrinter(MAI, MII, MRI, isDarwin);
188 createPPCMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.cpp278 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
286 if (MRI.livein_empty()) {
291 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
292 LE = MRI.livein_end();
H A DR600MachineScheduler.cpp33 MRI = &DAG->MRI;
216 return MRI->getRegClass(Reg) == RC;
375 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
378 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
381 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
384 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.cpp97 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
102 MRI.getDwarfRegNum(SystemZ::R15D, true),
179 const MCRegisterInfo &MRI,
181 return new SystemZInstPrinter(MAI, MII, MRI);
175 createSystemZMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp67 MachineRegisterInfo &MRI = MF.getRegInfo(); local
79 MRI.setPhysRegUsed(SystemZ::ArgGPRs[I]);
84 MRI.setPhysRegUsed(SystemZ::R11D);
89 MRI.setPhysRegUsed(SystemZ::R14D);
98 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) {
99 MRI.setPhysRegUsed(SystemZ::R15D);
318 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local
339 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
366 unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
392 unsigned DwarfReg = MRI
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H A DSystemZInstrInfo.cpp419 const MachineRegisterInfo *MRI) {
422 return MRI->getUniqueVRegDef(Reg);
433 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) { argument
434 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
443 const MachineRegisterInfo *MRI,
446 MachineInstr *RLL = getDef(SrcReg, MRI);
449 RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
474 eraseIfDead(LGFR, MRI);
418 getDef(unsigned Reg, const MachineRegisterInfo *MRI) argument
442 removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI) argument
679 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local
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/external/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp144 MachineRegisterInfo *MRI; member in class:__anon25935::SSACCmpConv
196 MRI = &MF.getRegInfo();
266 return MRI->use_nodbg_empty(DstReg);
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
604 MRI->constrainRegClass(HeadCond[2].getReg(),
651 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
654 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
729 MachineRegisterInfo *MRI; member in class:__anon25936::AArch64ConditionalCompares
898 MRI = &MF.getRegInfo();
/external/llvm/tools/llvm-mc/
H A Dllvm-mc.cpp387 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
388 assert(MRI && "Unable to create target register info!");
390 std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
405 MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr);
452 TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI);
461 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
462 MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
472 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
473 MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp431 const MCRegisterInfo &MRI; member in class:__anon26170::DarwinX86AsmBackend
482 assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
530 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
720 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, argument
722 : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
733 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, argument
735 : DarwinX86AsmBackend(T, MRI, CPU, false) {}
753 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, argument
755 : DarwinX86AsmBackend(T, MRI, CP
804 createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
820 createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h141 const MachineRegisterInfo *MRI) const override;
198 const MachineRegisterInfo *MRI) const override;
210 unsigned Reg, MachineRegisterInfo *MRI) const override;
277 const MachineRegisterInfo *MRI,
390 const MachineRegisterInfo &MRI);
415 const ARMBaseRegisterInfo& MRI,
/external/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp223 const MCRegisterInfo &MRI,
226 return(new HexagonInstPrinter(MAI, MII, MRI));
219 createHexagonMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument

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