Searched refs:SP (Results 101 - 125 of 204) sorted by relevance

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/external/libhevc/decoder/arm/
H A Dihevcd_fmt_conv_420sp_to_rgba8888.s91 STMFD SP!,{R4-R12,LR}
448 LDMFD SP!,{R4-R12,PC}
/external/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfDebug.h357 DIE &updateSubprogramScopeDIE(DwarfCompileUnit &SPCU, DISubprogram SP);
666 void addSubprogramNames(DISubprogram SP, DIE &Die);
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp355 if (GRDest && SrcReg == XCore::SP) {
360 if (DestReg == XCore::SP && GRSrc) {
H A DXCoreRegisterInfo.cpp236 Reserved.set(XCore::SP);
328 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
H A DXCoreFrameLowering.cpp91 /// The SP register is moved in steps of 'MaxImmU16' towards the bottom of the
93 /// IfNeededExtSP emits the necessary EXTSP instructions to move the SP only
96 /// \param [in,out] Adjusted the current SP offset from the top of the frame.
114 /// The SP register is moved in steps of 'MaxImmU16' towards the top of the
116 /// IfNeededLDAWSP emits the necessary LDAWSP instructions to move the SP only
119 /// \param [in,out] RemainingAdj the current SP offset from the top of the
129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
188 /// The SP will be adjusted at the same time, thus the SpillList must be ordered
245 // We will adjust the SP in stages towards the final FrameSize.
304 // Set the FP from the SP
[all...]
/external/llvm/include/llvm/IR/
H A DDebugInfo.h815 NamedMDNode *getOrInsertFnSpecificMDNode(Module &M, DISubprogram SP);
819 NamedMDNode *getFnSpecificMDNode(const Module &M, DISubprogram SP);
875 void processSubprogram(DISubprogram SP);
886 bool addSubprogram(DISubprogram SP);
H A DPatternMatch.h51 OneUse_match(const SubPattern_t &SP) : SubPattern(SP) {} argument
643 Exact_match(const SubPattern_t &SP) : SubPattern(SP) {} argument
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp72 // Initial state of the frame pointer is SP.
73 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
/external/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp68 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
/external/nist-sip/java/gov/nist/javax/sip/header/
H A DAuthenticationHeader.java158 return this.scheme + SP + parameters.encode();
H A DSIPHeaderList.java176 buffer.append(headerName).append(Separators.COLON).append(Separators.SP);
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1361 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
1362 // If either operand is SP, expand to ADD #0.
1445 .addReg(AArch64::SP, RegState::Define)
1447 .addReg(AArch64::SP)
1450 .addReg(AArch64::SP, RegState::Define)
1452 .addReg(AArch64::SP)
1623 assert(SrcReg != AArch64::SP);
1721 assert(DestReg != AArch64::SP);
1793 // slightly if DestReg is SP whic
[all...]
/external/openfst/src/include/fst/extensions/pdt/
H A Dexpand.h362 reverse_shortest_path_ = new SP(
477 typedef PdtShortestPath<Arc, FifoQueue<StateId> > SP; typedef in class:fst::PrunedExpand
478 typedef typename SP::CloseParenMultimap ParenMultimap;
479 SP *reverse_shortest_path_; // Shortest path for rfst_
549 typename SP::SearchState s(source + 1, dest + 1);
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp164 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
178 if (MI->getOperand(2).getReg() == ARM::SP &&
193 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
207 if (MI->getOperand(2).getReg() == ARM::SP &&
222 if (MI->getOperand(0).getReg() == ARM::SP) {
235 if (MI->getOperand(0).getReg() == ARM::SP) {
/external/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp117 // Look for inline asm that clobbers the SP register.
121 unsigned SP = TLI->getStackPointerRegisterToSaveRestore(); local
132 if (PhysReg.first == SP)
/external/mp4parser/isoparser/src/main/java/com/googlecode/mp4parser/authoring/tracks/
H A DH264TrackImpl.java428 P, B, I, SP, SI enum constant in enum:H264TrackImpl.SliceHeader.SliceType
464 slice_type = SliceType.SP;
/external/nist-sip/java/gov/nist/core/
H A DGenericObject.java54 protected static final String SP = Separators.SP; field in class:GenericObject
/external/valgrind/main/exp-bbv/tests/arm-linux/
H A Dll.S321 stmfd SP!,{LR} @ store return address on stack
348 ldmfd SP!,{LR} @ restore return address from stack
378 stmfd SP!,{r10,LR} @ store return address on stack
393 ldmfd SP!,{r10,LR} @ restore return address from stack
/external/clang/lib/StaticAnalyzer/Core/
H A DPathDiagnostic.cpp669 } else if (Optional<StmtPoint> SP = P.getAs<StmtPoint>()) {
670 S = SP->getStmt();
695 if (Optional<StmtPoint> SP = P.getAs<StmtPoint>())
696 return SP->getStmt();
H A DBugReporterVisitors.cpp183 if (Optional<StmtPoint> SP = Node->getLocationAs<StmtPoint>())
184 if (SP->getStmt() == S)
242 Optional<StmtPoint> SP = N->getLocationAs<StmtPoint>();
243 if (!SP)
246 const ReturnStmt *Ret = dyn_cast<ReturnStmt>(SP->getStmt());
/external/llvm/lib/Transforms/Utils/
H A DBasicBlockUtils.cpp253 if (BasicBlock *SP = Succ->getSinglePredecessor()) {
256 assert(SP == BB && "CFG broken");
257 SP = nullptr;
/external/llvm/test/MC/ARM/
H A Dbasic-thumb-instructions.s56 @ ADD (SP plus immediate)
76 @ ADD (SP plus register)
610 @ SUB (SP minus immediate)
/external/clang/tools/clang-format/
H A Dgit-clang-format338 --index-info", such as "<mode> <SP> <sha1> <TAB> <filename>". Any other mode
/external/libhevc/common/arm/
H A Dihevc_sao_band_offset_luma.s229 LDMFD sp!,{r4-r12,r15} @Reload the registers from SP
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp250 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);

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