/external/libhevc/decoder/arm/ |
H A D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 91 STMFD SP!,{R4-R12,LR} 448 LDMFD SP!,{R4-R12,PC}
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DwarfDebug.h | 357 DIE &updateSubprogramScopeDIE(DwarfCompileUnit &SPCU, DISubprogram SP); 666 void addSubprogramNames(DISubprogram SP, DIE &Die);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 355 if (GRDest && SrcReg == XCore::SP) { 360 if (DestReg == XCore::SP && GRSrc) {
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H A D | XCoreRegisterInfo.cpp | 236 Reserved.set(XCore::SP); 328 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
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H A D | XCoreFrameLowering.cpp | 91 /// The SP register is moved in steps of 'MaxImmU16' towards the bottom of the 93 /// IfNeededExtSP emits the necessary EXTSP instructions to move the SP only 96 /// \param [in,out] Adjusted the current SP offset from the top of the frame. 114 /// The SP register is moved in steps of 'MaxImmU16' towards the top of the 116 /// IfNeededLDAWSP emits the necessary LDAWSP instructions to move the SP only 119 /// \param [in,out] RemainingAdj the current SP offset from the top of the 129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm); 188 /// The SP will be adjusted at the same time, thus the SpillList must be ordered 245 // We will adjust the SP in stages towards the final FrameSize. 304 // Set the FP from the SP [all...] |
/external/llvm/include/llvm/IR/ |
H A D | DebugInfo.h | 815 NamedMDNode *getOrInsertFnSpecificMDNode(Module &M, DISubprogram SP); 819 NamedMDNode *getFnSpecificMDNode(const Module &M, DISubprogram SP); 875 void processSubprogram(DISubprogram SP); 886 bool addSubprogram(DISubprogram SP);
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H A D | PatternMatch.h | 51 OneUse_match(const SubPattern_t &SP) : SubPattern(SP) {} argument 643 Exact_match(const SubPattern_t &SP) : SubPattern(SP) {} argument
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 72 // Initial state of the frame pointer is SP. 73 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 68 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
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/external/nist-sip/java/gov/nist/javax/sip/header/ |
H A D | AuthenticationHeader.java | 158 return this.scheme + SP + parameters.encode();
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H A D | SIPHeaderList.java | 176 buffer.append(headerName).append(Separators.COLON).append(Separators.SP);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 1361 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) { 1362 // If either operand is SP, expand to ADD #0. 1445 .addReg(AArch64::SP, RegState::Define) 1447 .addReg(AArch64::SP) 1450 .addReg(AArch64::SP, RegState::Define) 1452 .addReg(AArch64::SP) 1623 assert(SrcReg != AArch64::SP); 1721 assert(DestReg != AArch64::SP); 1793 // slightly if DestReg is SP whic [all...] |
/external/openfst/src/include/fst/extensions/pdt/ |
H A D | expand.h | 362 reverse_shortest_path_ = new SP( 477 typedef PdtShortestPath<Arc, FifoQueue<StateId> > SP; typedef in class:fst::PrunedExpand 478 typedef typename SP::CloseParenMultimap ParenMultimap; 479 SP *reverse_shortest_path_; // Shortest path for rfst_ 549 typename SP::SearchState s(source + 1, dest + 1);
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 164 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 178 if (MI->getOperand(2).getReg() == ARM::SP && 193 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 207 if (MI->getOperand(2).getReg() == ARM::SP && 222 if (MI->getOperand(0).getReg() == ARM::SP) { 235 if (MI->getOperand(0).getReg() == ARM::SP) {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 117 // Look for inline asm that clobbers the SP register. 121 unsigned SP = TLI->getStackPointerRegisterToSaveRestore(); local 132 if (PhysReg.first == SP)
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/external/mp4parser/isoparser/src/main/java/com/googlecode/mp4parser/authoring/tracks/ |
H A D | H264TrackImpl.java | 428 P, B, I, SP, SI enum constant in enum:H264TrackImpl.SliceHeader.SliceType 464 slice_type = SliceType.SP;
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/external/nist-sip/java/gov/nist/core/ |
H A D | GenericObject.java | 54 protected static final String SP = Separators.SP; field in class:GenericObject
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/external/valgrind/main/exp-bbv/tests/arm-linux/ |
H A D | ll.S | 321 stmfd SP!,{LR} @ store return address on stack 348 ldmfd SP!,{LR} @ restore return address from stack 378 stmfd SP!,{r10,LR} @ store return address on stack 393 ldmfd SP!,{r10,LR} @ restore return address from stack
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | PathDiagnostic.cpp | 669 } else if (Optional<StmtPoint> SP = P.getAs<StmtPoint>()) { 670 S = SP->getStmt(); 695 if (Optional<StmtPoint> SP = P.getAs<StmtPoint>()) 696 return SP->getStmt();
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H A D | BugReporterVisitors.cpp | 183 if (Optional<StmtPoint> SP = Node->getLocationAs<StmtPoint>()) 184 if (SP->getStmt() == S) 242 Optional<StmtPoint> SP = N->getLocationAs<StmtPoint>(); 243 if (!SP) 246 const ReturnStmt *Ret = dyn_cast<ReturnStmt>(SP->getStmt());
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/external/llvm/lib/Transforms/Utils/ |
H A D | BasicBlockUtils.cpp | 253 if (BasicBlock *SP = Succ->getSinglePredecessor()) { 256 assert(SP == BB && "CFG broken"); 257 SP = nullptr;
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/external/llvm/test/MC/ARM/ |
H A D | basic-thumb-instructions.s | 56 @ ADD (SP plus immediate) 76 @ ADD (SP plus register) 610 @ SUB (SP minus immediate)
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/external/clang/tools/clang-format/ |
H A D | git-clang-format | 338 --index-info", such as "<mode> <SP> <sha1> <TAB> <filename>". Any other mode
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/external/libhevc/common/arm/ |
H A D | ihevc_sao_band_offset_luma.s | 229 LDMFD sp!,{r4-r12,r15} @Reload the registers from SP
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 250 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
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