Searched defs:MBB (Results 126 - 150 of 191) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp73 bool processBlock(MachineBasicBlock &MBB);
99 // Return true if CC is live out of MBB.
100 static bool isCCLiveOut(MachineBasicBlock &MBB) { argument
101 for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI)
330 MachineBasicBlock &MBB = *Compare->getParent(); local
331 MachineBasicBlock::iterator MBBI = Compare, MBBE = MBB.begin();
424 // Process all comparison instructions in MBB. Return true if something
426 bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) { argument
432 bool CompleteCCUsers = !isCCLiveOut(MBB);
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/external/mesa3d/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp49 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
58 BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
163 findFirstPredicateSetterFrom(MachineBasicBlock &MBB, argument
166 while (I != MBB.begin()) {
177 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, argument
186 MachineBasicBlock::iterator I = MBB.end();
187 if (I == MBB.begin())
191 if (I == MBB.begin())
204 if (I == MBB
261 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
367 isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, const BranchProbability &Probability) const argument
387 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, const BranchProbability &Probability) const argument
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/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h98 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB, argument
100 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
417 MachineBasicBlock &MBB; member in class:llvm::MIBundleBuilder
426 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
432 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
445 : MBB(*MI->getParent()), Begin(MI), End(getBundleEnd(MI)) {}
448 MachineBasicBlock &getMBB() const { return MBB; }
464 MBB.insert(I, MI);
482 /// Insert MI into MBB by prepending it to the instructions in the bundle.
488 /// Insert MI into MBB b
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H A DMachineOperand.h154 MachineBasicBlock *MBB; // For MO_MachineBasicBlock. member in union:llvm::MachineOperand::__anon25488
424 return Contents.MBB;
522 void setMBB(MachineBasicBlock *MBB) {
524 Contents.MBB = MBB;
601 static MachineOperand CreateMBB(MachineBasicBlock *MBB,
604 Op.setMBB(MBB);
H A DSlotIndexes.h349 /// MBBRanges - Map MBB number to (start, stop) indexes.
353 /// and MBB id.
392 void repairIndexesInRange(MachineBasicBlock *MBB,
443 const MachineBasicBlock *MBB = MI->getParent(); local
444 assert(MBB && "MI must be inserted inna basic block");
445 MachineBasicBlock::const_iterator I = MI, B = MBB->begin();
448 return getMBBStartIdx(MBB);
460 const MachineBasicBlock *MBB = MI->getParent(); local
461 assert(MBB && "MI must be inserted inna basic block");
462 MachineBasicBlock::const_iterator I = MI, E = MBB
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H A DMachineBasicBlock.h408 /// transferSuccessors - Transfers all the successors from MBB to this
418 /// isPredecessor - Return true if the specified MBB is a predecessor of this
420 bool isPredecessor(const MachineBasicBlock *MBB) const;
422 /// isSuccessor - Return true if the specified MBB is a successor of this
424 bool isSuccessor(const MachineBasicBlock *MBB) const;
426 /// isLayoutSuccessor - Return true if the specified MBB will be emitted
428 /// falling through, control will transfer to the specified MBB. Note
429 /// that MBB need not be a successor at all, for example if this block
431 bool isLayoutSuccessor(const MachineBasicBlock *MBB) const;
446 /// SkipPHIsAndLabels - Return the first instruction in MBB afte
770 MachineBasicBlock &MBB; member in class:llvm::MachineInstrSpan
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/external/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp140 /// Return true if all non-terminator instructions in MBB can be safely
142 bool canSpeculateInstrs(MachineBasicBlock *MBB);
165 /// canConvertIf - If the sub-CFG headed by MBB can be if-converted,
167 bool canConvertIf(MachineBasicBlock *MBB);
176 /// canSpeculateInstrs - Returns true if all the instructions in MBB can safely
184 bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { argument
187 if (!MBB->livein_empty()) {
188 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
196 for (MachineBasicBlock::iterator I = MBB->begin(),
197 E = MBB
340 canConvertIf(MachineBasicBlock *MBB) argument
490 MachineBasicBlock *MBB = PI.PHI->getOperand(i-1).getMBB(); local
762 tryConvertIf(MachineBasicBlock *MBB) argument
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H A DExecutionDepsFix.cpp347 void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) { argument
358 // Set up LiveRegs to represent registers entering MBB.
369 if (MBB->pred_empty()) {
370 for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
371 e = MBB->livein_end(); i != e; ++i) {
380 DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
385 for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
386 pe = MBB->pred_end(); pi != pe; ++pi) {
422 DEBUG(dbgs() << "BB#" << MBB->getNumber()
426 void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) { argument
546 processUndefReads(MachineBasicBlock *MBB) argument
751 MachineBasicBlock *MBB = *MBBI; local
765 MachineBasicBlock *MBB = Loops[i]; local
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H A DLiveVariables.cpp60 LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
62 if (Kills[i]->getParent() == MBB)
94 MachineBasicBlock *MBB,
96 unsigned BBNum = MBB->getNumber();
101 if (VRInfo.Kills[i]->getParent() == MBB) {
106 if (MBB == DefBlock) return; // Terminate recursion
114 assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
115 WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
120 MachineBasicBlock *MBB) {
92 MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *MBB, std::vector<MachineBasicBlock*> &WorkList) argument
118 MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *MBB) argument
131 HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr *MI) argument
531 MachineBasicBlock *MBB = *DFI; local
715 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument
733 isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) argument
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H A DPeepholeOptimizer.cpp130 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
131 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
138 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
263 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, argument
340 if (UseMBB == MBB) {
348 } else if (Aggressive && DT->dominates(MBB, UseMBB)) {
353 // Both will be live out of the def MBB anyway. Don't extend live range of
414 MachineBasicBlock *MBB) {
644 bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB, argument
684 MachineBasicBlock *MBB local
413 optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB) argument
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H A DRegAllocFast.cpp64 MachineBasicBlock *MBB; member in class:__anon25790::RAFast
291 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
305 if (MI == MBB->end()) {
311 MachineBasicBlock *MBB = DBG->getParent(); local
313 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
630 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
787 DEBUG(dbgs() << "\nAllocating " << *MBB);
792 MachineBasicBlock::iterator MII = MBB->begin();
795 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
796 E = MBB
868 MachineBasicBlock *MBB = MI->getParent(); local
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H A DTailDuplication.cpp119 bool TailDuplicateAndUpdate(MachineBasicBlock *MBB,
123 void RemoveDeadBlock(MachineBasicBlock *MBB);
163 MachineBasicBlock *MBB = I; local
164 SmallSetVector<MachineBasicBlock*, 8> Preds(MBB->pred_begin(),
165 MBB->pred_end());
166 MachineBasicBlock::iterator MI = MBB->begin();
167 while (MI != MBB->end()) {
182 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
192 dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber()
199 dbgs() << "Malformed PHI in BB#" << MBB
211 TailDuplicateAndUpdate(MachineBasicBlock *MBB, bool IsSimple, MachineFunction &MF) argument
324 MachineBasicBlock *MBB = I++; local
967 RemoveDeadBlock(MachineBasicBlock *MBB) argument
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H A DTargetInstrInfo.cpp62 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB, argument
103 MachineBasicBlock *MBB = Tail->getParent(); local
105 // Remove all the old successors of MBB from the CFG.
106 while (!MBB->succ_empty())
107 MBB->removeSuccessor(MBB->succ_begin());
109 // Remove all the dead instructions from the end of MBB.
110 MBB->erase(Tail, MBB->end());
112 // If MBB is
314 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
455 MachineBasicBlock *MBB = MI->getParent(); local
522 MachineBasicBlock &MBB = *MI->getParent(); local
646 isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const argument
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/external/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp227 /// Given a couple (MBB, reg) get the corresponding set of instruction from
234 const MachineBasicBlock &MBB, unsigned reg,
237 BlockToSetOfInstrsPerColor::iterator it = sets.find(&MBB);
241 result = sets[&MBB] = new SetOfMachineInstr[nbRegs];
290 for (MachineBasicBlock &MBB : MF) {
291 const MachineInstr **&BBGen = Gen[&MBB];
295 BitVector &BBKillSet = Kill[&MBB];
297 for (const MachineInstr &MI : MBB) {
316 getSet(ReachableUses, MBB, CurReg, NbReg).insert(&MI);
368 if (!ADRPMode && DummyOp && !MBB
233 getSet(BlockToSetOfInstrsPerColor &sets, const MachineBasicBlock &MBB, unsigned reg, unsigned nbRegs) argument
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H A DAArch64FrameLowering.cpp109 MachineFunction &MF, MachineBasicBlock &MBB,
142 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
148 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
151 MBB.erase(I);
155 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
157 MachineFunction &MF = *MBB.getParent();
162 DebugLoc DL = MBB.findDebugLoc(MBBI);
197 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
203 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB. local
204 MachineBasicBlock::iterator MBBI = MBB
108 eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
615 spillCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
691 restoreCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
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H A DAArch64InstrInfo.cpp38 const MachineBasicBlock &MBB = *MI->getParent(); local
39 const MachineFunction *MF = MBB.getParent();
92 bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, argument
98 MachineBasicBlock::iterator I = MBB.end();
99 if (I == MBB.begin())
103 if (I == MBB.begin())
115 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
139 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
151 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
225 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) cons
255 instantiateCondBranch( MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB, const SmallVectorImpl<MachineOperand> &Cond) const argument
271 InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
369 canInsertSelect( const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
410 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
662 MachineBasicBlock *MBB = Instr->getParent(); local
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/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp398 emitLoadConstPool(MachineBasicBlock &MBB, argument
404 MachineFunction &MF = *MBB.getParent();
411 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
580 materializeFrameBaseRegister(MachineBasicBlock *MBB, argument
583 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
587 MachineBasicBlock::iterator Ins = MBB->begin();
589 if (Ins != MBB->end())
592 const MachineFunction &MF = *MBB->getParent();
593 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
598 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, In
607 MachineBasicBlock &MBB = *MI.getParent(); local
706 MachineBasicBlock &MBB = *MI.getParent(); local
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H A DThumb2SizeReduction.cpp156 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
159 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
164 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
170 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
175 bool ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
179 bool ReduceMBB(MachineBasicBlock &MBB);
365 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, argument
494 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
520 MBB.erase_instr(MI);
526 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInst argument
628 ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop) argument
746 ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop) argument
889 ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI, bool LiveCPSR, bool IsSelfLoop) argument
914 ReduceMBB(MachineBasicBlock &MBB) argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp129 MachineBasicBlock *MBB) override;
215 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
216 MBB != MBBe; ++MBB) {
217 MachineBasicBlock::iterator End = MBB->end();
218 MachineBasicBlock::iterator MI = MBB->begin();
223 MBB->erase(DeleteMI);
224 End = MBB->end();
232 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
233 MBB !
957 ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) argument
1355 MachineBasicBlock *MBB = MI->getParent(); local
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/external/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp81 /// Set bits in Uses corresponding to MBB's live-out registers except for
83 void addLiveOut(const MachineBasicBlock &MBB,
197 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
208 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
214 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
216 /// This function searches MBB in the forward direction for an instruction
218 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
220 /// This function searches one of MBB's successor blocks for an instruction
223 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
225 /// Pick a successor block of MBB
268 addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) argument
338 addLiveOut(const MachineBasicBlock &MBB, const MachineBasicBlock &SuccBB) argument
494 runOnMachineBasicBlock(MachineBasicBlock &MBB) argument
534 searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, RegDefsUses &RegDU, InspectMemInstr& IM, IterTy &Filler) const argument
570 searchBackward(MachineBasicBlock &MBB, Iter Slot) const argument
589 searchForward(MachineBasicBlock &MBB, Iter Slot) const argument
609 searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const argument
668 getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const argument
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H A DMipsSEInstrInfo.cpp82 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
110 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
131 BuildMI(MBB, I, DL, get(Mips::WRDSP))
170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, argument
188 if (I != MBB.end()) DL = I->getDebugLoc();
189 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
221 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
226 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, argument
230 if (I != MBB
267 MachineBasicBlock &MBB = *MI->getParent(); local
360 adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
379 loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned *NewImm) const argument
430 expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
453 expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned NewOpc) const argument
459 expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned LoOpc, unsigned HiOpc, bool HasExplicitDef) const argument
488 expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned CvtOpc, unsigned MovOpc, bool IsI64) const argument
512 expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool FP64) const argument
592 expandEhReturn(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp275 MachineBasicBlock &MBB = *MI.getParent(); local
277 MachineFunction &MF = *MBB.getParent();
308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
312 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
316 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
333 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
338 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
344 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
348 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
358 BuildMI(MBB, I
395 MachineBasicBlock &MBB = *MI.getParent(); local
439 MachineBasicBlock &MBB = *MI.getParent(); local
512 MachineBasicBlock &MBB = *MI.getParent(); local
555 MachineBasicBlock &MBB = *MI.getParent(); local
602 MachineBasicBlock &MBB = *MI.getParent(); local
627 MachineBasicBlock &MBB = *MI.getParent(); local
705 MachineBasicBlock &MBB = *MI.getParent(); local
943 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
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/external/llvm/lib/Target/R600/
H A DR600ControlFlowFinalizer.cpp315 MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I) argument
322 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
335 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
371 MachineBasicBlock *MBB = InsertPos->getParent(); local
375 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
384 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I) argument
389 for (MachineBasicBlock::instr_iterator E = MBB.instr_end(); I != E;) {
420 MachineInstr *MILit = BuildMI(MBB, I, I->getDebugLoc(),
487 MachineBasicBlock &MBB variable
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/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp61 static void EmitDefCfaRegister(MachineBasicBlock &MBB, argument
67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
71 static void EmitDefCfaOffset(MachineBasicBlock &MBB, argument
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
81 static void EmitCfiOffset(MachineBasicBlock &MBB, argument
87 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
97 static void IfNeededExtSP(MachineBasicBlock &MBB, argument
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
121 static void IfNeededLDAWSP(MachineBasicBlock &MBB, argument
176 getFrameIndexMMO(MachineBasicBlock &MBB, int FrameIndex, unsigned flags) argument
191 RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc dl, const TargetInstrInfo &TII, int &RemainingAdj, SmallVectorImpl<StackSlotInfo> &SpillList) argument
223 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB local
408 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
444 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
479 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
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/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h217 virtual void reMaterialize(MachineBasicBlock &MBB,
273 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
298 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, argument
305 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
308 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
322 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
352 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, argument
363 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, argument
386 /// instruction latencies in the specified MBB to enable if-conversion.
391 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigne argument
429 canInsertSelect(const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
453 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
514 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
526 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
539 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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