/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 75 unsigned GetX86RegNum(const MCOperand &MO) const { 76 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 770 const MCOperand &MO = MI.getOperand(CurOp); local 771 if (MO.isReg()) { 772 if (X86II::isX86_64ExtendedReg(MO.getReg())) 774 if (X86II::is32ExtendedReg(MO.getReg())) 1028 const MCOperand &MO = MI.getOperand(i); local 1029 if (!MO.isReg()) continue; 1030 unsigned Reg = MO.getReg(); 1045 const MCOperand &MO local 1057 const MCOperand &MO = MI.getOperand(i); local 1079 const MCOperand &MO = MI.getOperand(i); local 1094 const MCOperand &MO = MI.getOperand(i); local 1542 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | IfConversion.cpp | 1423 const MachineOperand &MO = FI->getOperand(i); local 1424 if (!MO.isReg()) 1426 unsigned Reg = MO.getReg(); 1429 if (MO.isDef()) { 1512 const MachineOperand &MO = MI->getOperand(i); local 1513 if (!MO.isReg()) 1515 unsigned Reg = MO.getReg(); 1518 if (MO.isDef() && !LaterRedefs.count(Reg))
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H A D | MachineInstr.cpp | 215 hash_code llvm::hash_value(const MachineOperand &MO) { argument 216 switch (MO.getType()) { 219 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); 221 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm()); 223 return hash_combine(MO 761 addMemOperand(MachineFunction &MF, MachineMemOperand *MO) argument 813 const MachineOperand &MO = getOperand(i); local 881 const MachineOperand &MO = getOperand(i); local 1027 const MachineOperand &MO = getOperand(OpIdx); local 1038 const MachineOperand &MO = getOperand(OpIdx); local 1068 const MachineOperand &MO = getOperand(i); local 1096 const MachineOperand &MO = getOperand(i); local 1122 const MachineOperand &MO = getOperand(i); local 1203 const MachineOperand &MO = getOperand(OpIdx); local 1261 MachineOperand &MO = getOperand(i); local 1275 MachineOperand &MO = getOperand(i); local 1282 MachineOperand &MO = getOperand(i); local 1426 const MachineOperand &MO = getOperand(i); local 1441 const MachineOperand &MO = MI->getOperand(i); local 1532 const MachineOperand &MO = getOperand(i); local 1693 MachineOperand &MO = getOperand(i); local 1748 MachineOperand &MO = getOperand(i); local 1766 MachineOperand &MO = getOperand(i); local 1812 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo); local 1817 const MachineOperand &MO = getOperand(i); local 1832 MachineOperand &MO = getOperand(i); local 1866 const MachineOperand &MO = MI->getOperand(i); local [all...] |
H A D | MachineVerifier.cpp | 202 void visitMachineOperand(const MachineOperand *MO, unsigned MONum); 211 void report(const char *msg, const MachineOperand *MO, unsigned MONum); 223 void checkLiveness(const MachineOperand *MO, unsigned MONum); 412 const MachineOperand *MO, unsigned MONum) { 413 assert(MO); 414 report(msg, MO->getParent()); 416 MO->print(*OS, TM); 751 const MachineOperand &MO = MI->getOperand(OpNo); local 753 if (!MO.isImm()) 755 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO 411 report(const char *msg, const MachineOperand *MO, unsigned MONum) argument 767 const MachineOperand &MO = MI->getOperand(OpNo); local 816 visitMachineOperand(const MachineOperand *MO, unsigned MONum) argument 986 checkLiveness(const MachineOperand *MO, unsigned MONum) argument [all...] |
H A D | RegisterCoalescer.cpp | 624 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) { 625 MachineInstr *UseMI = MO.getParent(); 626 unsigned OpNo = &MO - &UseMI->getOperand(0); 816 MachineOperand &MO = NewMI->getOperand(i); local 817 if (MO.isReg()) { 818 assert(MO.isDef() && MO.isImplicit() && MO.isDead() && 819 TargetRegisterInfo::isPhysicalRegister(MO.getReg())); 820 NewMIImplDefs.push_back(MO 878 MachineOperand &MO = CopyMI->getOperand(i); local 983 MachineOperand &MO = UseMI->getOperand(Ops[i]); local [all...] |
H A D | ScheduleDAGInstrs.cpp | 222 const MachineOperand &MO = ExitMI->getOperand(i); local 223 if (!MO.isReg() || MO.isDef()) continue; 224 unsigned Reg = MO.getReg(); 231 if (MO.readsReg()) // ignore undef operands 250 /// MO is an operand of SU's instruction that defines a physical register. Add 253 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); local 254 assert(MO.isDef() && "expect physreg def"); 259 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 297 MachineOperand &MO local 815 const MachineOperand &MO = MI->getOperand(j); local 1073 toggleKillFlag(MachineInstr *MI, MachineOperand &MO) argument 1125 MachineOperand &MO = MI->getOperand(i); local 1146 MachineOperand &MO = MI->getOperand(i); local 1181 MachineOperand &MO = MI->getOperand(i); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMConstantIslandPass.cpp | 1906 const MachineOperand &MO = AddrMI->getOperand(k); local 1907 if (!MO.isReg() || !MO.getReg()) 1909 if (MO.isDef() && MO.getReg() != BaseReg) { 1913 if (MO.isUse() && !MO.isKill() && MO.getReg() != IdxReg) {
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H A D | ARMLoadStoreOptimizer.cpp | 354 MachineOperand &MO = local 357 Offset = MO.getImm() - WordOffset * getImmScale(Opc); 359 MO.setImm(Offset); 366 MachineOperand &MO = local 369 MO.getImm() + WordOffset * 4 : 370 MO.getImm() - WordOffset * 4 ; 372 MO.setImm(Offset); 649 for (MIOperands MO(memOps[i].MBBI); MO.isValid(); ++MO) { 745 const MachineOperand &MO = MemOps[i].MBBI->getOperand(0); local 781 const MachineOperand &MO = MI->getOperand(i); local 1209 MachineOperand &MO = MI->getOperand(0); local 1238 MachineOperand &MO = MI->getOperand(0); local 1530 const MachineOperand &MO = MBBI->getOperand(0); local 1710 MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1); local 1839 MachineOperand &MO = I->getOperand(j); local [all...] |
H A D | ARMFastISel.cpp | 236 const MachineOperand &MO = MI->getOperand(i); local 237 if (!MO.isReg() || !MO.isDef()) continue; 238 if (MO.getReg() == ARM::CPSR)
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H A D | ARMBaseInstrInfo.cpp | 243 MachineOperand &MO = MI->getOperand(i); local 244 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 245 unsigned Reg = MO.getReg(); 248 if (MO.isDef()) { 250 if (MO.isDead()) 253 if (MO.isUse() && MO.isKill()) { 510 const MachineOperand &MO = MI->getOperand(i); local 511 if ((MO 545 const MachineOperand &MO = MI->getOperand(i); local 1699 const MachineOperand &MO = MI->getOperand(i); local 2392 const MachineOperand &MO = Instr.getOperand(IO); local 2507 const MachineOperand &MO = DefMI->getOperand(NumOps-1); local 4277 const MachineOperand &MO = MI->getOperand(OpNum); local 4336 const MachineOperand &MO = MI->getOperand(OpNum); local [all...] |
H A D | ARMISelLowering.cpp | 7525 const MachineOperand &MO = MI->getOperand(i); local 7526 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { 7528 if (MO.isDead()) 7547 MachineOperand &MO = MI->getOperand(ccOutIdx); local 7548 MO.setReg(ARM::CPSR); 7549 MO.setIsDef(true);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 182 /// \brief Get the immediate value referenced to by \p MO, either for 185 int64_t getImmediate(MachineOperand &MO); 190 void setImmediate(MachineOperand &MO, int64_t Val); 859 const MachineOperand &MO = MI->getOperand(i); local 860 if (!MO.isReg() || !MO.isDef()) 862 unsigned R = MO.getReg(); 896 const MachineOperand &MO = MI->getOperand(i); local 897 if (!MO.isReg() || !MO 951 const MachineOperand &MO = MI->getOperand(i); local 1170 MachineOperand &MO = In->getOperand(i); local 1204 getImmediate(MachineOperand &MO) argument 1218 setImmediate(MachineOperand &MO, int64_t Val) argument 1333 MachineOperand &MO = PredDef->getOperand(i); local 1399 MachineOperand &MO = PredDef->getOperand(i); local 1506 MachineOperand &MO = PN->getOperand(i+1); local [all...] |
H A D | HexagonInstrInfo.cpp | 614 // Use MO operand flags to determine if one of MI's operands 865 MachineOperand &MO = MI->getOperand(oper); local 873 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) { 876 if (MO.isReg()) { 877 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(), 878 MO.isImplicit(), MO 1039 MachineOperand MO = MI->getOperand(oper); local 1631 MachineOperand &MO = MI->getOperand(ExtOpNum); local 1682 const MachineOperand &MO = MI->getOperand(ExtOpNum); local [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 332 const MachineOperand &MO = MI->getOperand(OpNo); local 380 lowerImageHandleSymbol(MO.getImm(), MCOp); 384 lowerImageHandleSymbol(MO.getImm(), MCOp); 407 lowerImageHandleSymbol(MO.getImm(), MCOp); 430 lowerImageHandleSymbol(MO.getImm(), MCOp); 453 lowerImageHandleSymbol(MO.getImm(), MCOp); 551 lowerImageHandleSymbol(MO.getImm(), MCOp); 573 lowerImageHandleSymbol(MO.getImm(), MCOp); 600 const MachineOperand &MO = MI->getOperand(0); local 602 OutContext.GetOrCreateSymbol(Twine(MO 607 const MachineOperand &MO = MI->getOperand(i); local 622 lowerOperand(const MachineOperand &MO, MCOperand &MCOp) argument 919 printVecModifiedImmediate( const MachineOperand &MO, const char *Modifier, raw_ostream &O) argument 2389 const MachineOperand &MO = MI->getOperand(opNum); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 1244 const MachineOperand &MO = MI->getOperand(i); local 1247 if (MO.isReg()) { 1248 if (MO.isDef() && RC->contains(MO.getReg())) { 1249 Pred.push_back(MO); 1252 } else if (MO.isRegMask()) { 1255 if (MO.clobbersPhysReg(*I)) { 1256 Pred.push_back(MO);
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/external/llvm/lib/Target/R600/ |
H A D | SIInstrInfo.cpp | 511 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const { 512 if (MO.isImm()) 513 return isInlineConstant(APInt(32, MO.getImm(), true)); 515 if (MO.isFPImm()) { 516 APFloat FpImm = MO.getFPImm()->getValueAPF(); 523 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const { 524 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO); 604 const MachineOperand &MO local 760 MachineOperand &MO = MI->getOperand(OpIdx); local 906 MachineOperand &MO = MI->getOperand(Idx); local [all...] |
/external/chromium_org/third_party/libaddressinput/src/java/src/com/android/i18n/addressinput/ |
H A D | RegionDataConstants.java | 746 MO(new String[]{ enum constant in enum:RegionDataConstants.RegionDataEnum
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1740 MachineOperand &MO = Iter->getOperand(j); local 1741 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1743 if (!MO.isReg()) 1745 if (MO.getReg() == X86::EFLAGS) { 1746 if (MO.isUse()) 1786 MachineOperand &MO = Iter->getOperand(j); local 1789 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1791 if (MO 1832 MachineOperand &MO = MI->getOperand(i); local 3851 MachineOperand &MO = Sub->getOperand(i); local 3897 MachineOperand &MO = MI->getOperand(i); local 4020 MachineOperand &MO = MI->getOperand(i+2); local 4024 MachineOperand &MO = MI->getOperand(i); local 4040 MachineOperand &MO = MI->getOperand(i); local 4227 const MachineOperand &MO = MI->getOperand(0); local 4299 const MachineOperand &MO = MI->getOperand(OpNum); local 4633 MachineOperand &MO = NewMIs[0]->getOperand(i); local 4653 MachineOperand &MO = ImpOps[i]; local [all...] |
/external/qemu/disas/ |
H A D | ppc.c | 551 /* The MO field in an mbar instruction. */ 552 #define MO CT 4527 { "mbar", X(31,854), X_MASK, BOOKE, { MO } }, 548 #define MO macro
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 7878 MCOperand &MO = Inst.getOperand(1); local 7879 unsigned Mask = MO.getImm(); 7886 MO.setImm(Mask);
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/external/owasp/sanitizer/lib/htmlparser-1.3/ |
H A D | htmlparser-1.3-with-transitions.jar | META-INF/MANIFEST.MF nu/validator/htmlparser/tools/XSLT4HTML5XOM.class XSLT4HTML5XOM.java package nu. ... |
H A D | htmlparser-1.3.jar | META-INF/MANIFEST.MF nu/validator/htmlparser/tools/XSLT4HTML5XOM.class XSLT4HTML5XOM.java package nu. ... |