/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 160 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 194 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 766 MachineRegisterInfo *MRI = &MF.getRegInfo(); local 772 MRI->setPhysRegUsed(AArch64::FP); 773 MRI->setPhysRegUsed(AArch64::LR); 779 MRI->setPhysRegUsed(RegInfo->getBaseRegister()); 801 const bool OddRegUsed = MRI->isPhysRegUsed(OddReg); 802 const bool EvenRegUsed = MRI->isPhysRegUsed(EvenReg); 823 MRI->setPhysRegUsed(Reg); 877 MRI [all...] |
H A D | AArch64InstrInfo.cpp | 292 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) { argument 294 const MachineInstr *DefMI = MRI.getVRegDef(VReg); 305 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, argument 307 VReg = removeCopies(MRI, VReg); 311 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); 312 const MachineInstr *DefMI = MRI.getVRegDef(VReg); 335 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); 352 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); 374 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 376 RI.getCommonSubClass(MRI 415 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 669 MachineRegisterInfo *MRI = &MF->getRegInfo(); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 222 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 223 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 244 if (PairedPhys && MRI.isReserved(PairedPhys)) 260 if (!Paired || MRI.isReserved(Paired)) 269 MachineRegisterInfo *MRI = &MF.getRegInfo(); local 270 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 279 Hint = MRI->getRegAllocationHint(OtherReg); 282 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 341 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 353 if (!MRI 593 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAsmBackend.cpp | 805 const MCRegisterInfo &MRI, 838 const MCRegisterInfo &MRI, 840 return createARMAsmBackend(T, MRI, TT, CPU, true); 844 const MCRegisterInfo &MRI, 846 return createARMAsmBackend(T, MRI, TT, CPU, false); 850 const MCRegisterInfo &MRI, 852 return createARMAsmBackend(T, MRI, TT, CPU, true); 856 const MCRegisterInfo &MRI, 858 return createARMAsmBackend(T, MRI, TT, CPU, false); 804 createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU, bool isLittle) argument 837 createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument 843 createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument 849 createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument 855 createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 85 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI, argument 106 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), 107 E = MRI->use_end(); U != E;) { 218 MachineRegisterInfo *MRI = &MF.getRegInfo(); local 228 replaceUsesWithZeroReg(MRI, *I);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 956 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 957 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 981 MachineRegisterInfo &MRI = MF.getRegInfo(); 982 MRI.constrainRegClass(BaseReg,
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 283 const MachineRegisterInfo &MRI = MF->getRegInfo(); local 287 if (MRI.use_empty(reg))
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 431 const MCRegisterInfo &MRI; member in class:__anon26170::DarwinX86AsmBackend 482 assert(MRI.getLLVMRegNum(Inst.getRegister(), true) == 530 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 720 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, argument 722 : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) { 733 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, argument 735 : DarwinX86AsmBackend(T, MRI, CPU, false) {} 753 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, argument 755 : DarwinX86AsmBackend(T, MRI, CP 804 createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument 820 createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 227 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo(); local 268 unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true); 293 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true); 308 MRI->getDwarfRegNum(FramePtr, true)); 319 unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true); 329 MRI->getDwarfRegNum(SpillList[0].Reg, true), 332 MRI->getDwarfRegNum(SpillList[1].Reg, true),
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 977 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { argument 978 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); 980 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
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H A D | ScheduleDAG.h | 558 MachineRegisterInfo &MRI; // Virtual/real register map member in class:llvm::SUnit::ScheduleDAG
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/external/llvm/include/llvm/MC/ |
H A D | MCContext.h | 62 const MCRegisterInfo *MRI; member in class:llvm::MCContext 179 explicit MCContext(const MCAsmInfo *MAI, const MCRegisterInfo *MRI, 188 const MCRegisterInfo *getRegisterInfo() const { return MRI; }
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/external/llvm/include/llvm/Support/ |
H A D | TargetRegistry.h | 82 typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI, 105 const MCRegisterInfo &MRI, 120 const MCRegisterInfo &MRI, 123 const MCRegisterInfo &MRI, 283 MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, argument 287 return MCAsmInfoCtorFn(MRI, Triple); 361 MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, argument 365 return MCAsmBackendCtorFn(*this, MRI, Triple, CPU); 400 const MCRegisterInfo &MRI, 404 return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, ST 397 createMCInstPrinter(unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) const argument 409 createMCCodeEmitter(const MCInstrInfo &II, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) const argument 1088 Allocator(const Target &T, const MCRegisterInfo &MRI, StringRef Triple, StringRef CPU) argument [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 271 const MachineRegisterInfo *MRI = nullptr) const; 793 const MachineRegisterInfo *MRI) const { 805 const MachineRegisterInfo *MRI, 813 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 818 unsigned Reg, MachineRegisterInfo *MRI) const { 891 const MachineRegisterInfo *MRI, 804 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const argument 890 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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/external/llvm/lib/CodeGen/ |
H A D | BranchFolding.cpp | 196 MachineRegisterInfo &MRI = MF.getRegInfo(); local 197 if (MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF)) 200 MRI.invalidateLiveness();
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H A D | InlineSpiller.cpp | 68 MachineRegisterInfo &MRI; member in class:__anon25751::InlineSpiller 153 MRI(mf.getRegInfo()), 244 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg), 245 E = MRI.reg_instr_nodbg_end(); RI != E; ) { 284 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) { 745 MRI.getRegClass(SVI.SpillReg), &TRI); 780 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end(); 943 RI = MRI [all...] |
H A D | LiveDebugVariables.cpp | 247 MachineRegisterInfo &MRI, 252 void computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, 566 MachineRegisterInfo &MRI, LiveIntervals &LIS) { 575 for (MachineOperand &MO : MRI.use_nodbg_operands(LI->reg)) { 634 UserValue::computeIntervals(MachineRegisterInfo &MRI, argument 668 addDefsFromCopies(LI, LocNo, Kills, Defs, MRI, LIS); 563 addDefsFromCopies(LiveInterval *LI, unsigned LocNo, const SmallVectorImpl<SlotIndex> &Kills, SmallVectorImpl<std::pair<SlotIndex, unsigned> > &NewDefs, MachineRegisterInfo &MRI, LiveIntervals &LIS) argument
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H A D | LiveIntervalAnalysis.cpp | 112 MRI = &MF->getRegInfo(); 123 VirtRegIntervals.resize(MRI->getNumVirtRegs()); 149 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 193 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 195 if (MRI->reg_nodbg_empty(Reg)) 249 if (!MRI->reg_empty(*Supers)) 260 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg)) 332 I = MRI->reg_instr_begin(li->reg), E = MRI 726 const MachineRegisterInfo& MRI; member in class:LiveIntervals::HMEditor 734 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, const TargetRegisterInfo& TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags) argument [all...] |
H A D | MachineBasicBlock.cpp | 361 MachineRegisterInfo &MRI = getParent()->getRegInfo(); local 369 if (!MRI.constrainRegClass(VirtReg, RC)) 375 unsigned VirtReg = MRI.createVirtualRegister(RC); 880 MachineRegisterInfo *MRI = &getParent()->getRegInfo(); local 881 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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H A D | MachineFunction.cpp | 437 MachineRegisterInfo &MRI = getRegInfo(); local 438 unsigned VReg = MRI.getLiveInVirtReg(PReg); 440 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg); 452 VReg = MRI.createVirtualRegister(RC); 453 MRI.addLiveIn(PReg, VReg);
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H A D | MachineLICM.cpp | 69 MachineRegisterInfo *MRI; member in class:__anon25767::MachineLICM 332 MRI = &MF.getRegInfo(); 335 PreRegAlloc = MRI->isSSA(); 776 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) { argument 777 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg()); 786 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 831 bool isKill = isOperandKill(MO, MRI); 860 else if (!isNew && isOperandKill(MO, MRI)) { 941 if (!MRI->isConstantPhysReg(Reg, *I.getParent()->getParent())) 958 assert(MRI [all...] |
H A D | RegisterPressure.cpp | 85 PSetIterator PSetI = MRI->getPressureSets(RegUnits[i]); 99 decreaseSetPressure(CurrSetPressure, MRI->getPressureSets(RegUnits[I])); 190 MRI = &MF->getRegInfo(); 205 LiveRegs.VirtRegs.setUniverse(MRI->getNumVirtRegs()); 207 UntiedDefs.setUniverse(MRI->getNumVirtRegs()); 297 increaseSetPressure(LiveThruPressure, MRI->getPressureSets(Reg)); 314 const MachineRegisterInfo *MRI; member in class:RegisterOperands 324 TRI(tri), MRI(mri), IgnoreDead(ID) {} 349 else if (MRI->isAllocatable(Reg)) { 386 const MachineRegisterInfo *MRI) { 385 addPressureChange(unsigned RegUnit, bool IsDec, const MachineRegisterInfo *MRI) argument 411 collectPDiff(PressureDiff &PDiff, RegisterOperands &RegOpers, const MachineRegisterInfo *MRI) argument 882 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument [all...] |
H A D | SplitKit.cpp | 134 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 135 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg)) 330 MRI(vrm.getMachineFunction().getRegInfo()), 972 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()), 973 RE = MRI.reg_end(); RI != RE;) { 1119 ConEQ.Distribute(&dups[0], MRI);
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H A D | TwoAddressInstructionPass.cpp | 75 MachineRegisterInfo *MRI; member in class:__anon25830::TwoAddressInstructionPass 231 UI = MRI->use_nodbg_begin(SavedReg), 232 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 319 for (MachineOperand &MO : MRI->reg_operands(Reg)) { 402 const MachineRegisterInfo *MRI, 410 (allowFalsePositives || MRI->hasOneUse(Reg))) 416 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); 419 if (std::next(Begin) != MRI->def_end()) 452 MachineRegisterInfo *MRI, 456 if (!MRI 401 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument 451 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 37 const MCRegisterInfo &MRI, 39 : MCInstPrinter(MAI, MII, MRI) { 46 const MCRegisterInfo &MRI, 48 : AArch64InstPrinter(MAI, MII, MRI, STI) {} 1163 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || 1164 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) 1166 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || 1167 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) 1169 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || 1170 MRI 35 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 44 AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument [all...] |