Searched defs:dl (Results 126 - 133 of 133) sorted by relevance

123456

/external/chromium_org/third_party/sqlite/src/ext/fts2/
H A Dfts2.c6159 DataBuffer dl; local
6185 dataBufferInit(&dl, 0);
6187 dataBufferReset(&dl);
6188 dlcAddDoclist(pData[i].pCollector, &dl);
6190 pData[i].pTerm, pData[i].nTerm, dl.pData, dl.nData);
6196 dataBufferDestroy(&dl);
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp978 SDLoc dl, SelectionDAG &DAG) {
982 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1016 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1021 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1077 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1228 SDLoc dl(Sel);
1252 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1255 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1258 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1393 SDLoc dl(O
977 emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) argument
1020 getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) argument
4543 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) argument
5826 EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, SDLoc dl, SelectionDAG &DAG) argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1253 SDLoc dl, SelectionDAG &DAG,
1281 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1286 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1292 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1295 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1296 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1300 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1304 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1309 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1310 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MV
1250 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument
1336 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
1349 PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
1382 SDLoc &dl = CLI.DL; local
2079 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
2777 StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, const Value *OrigArg, unsigned InRegsParamRecordIdx, unsigned OffsetFromOrigArg, unsigned ArgOffset, unsigned ArgSize, bool ForceMutable, unsigned ByValStoreOffset, unsigned TotalArgRegsSaveSize) const argument
2883 VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, unsigned ArgOffset, unsigned TotalArgRegsSaveSize, bool ForceMutable) const argument
2905 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3991 getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) argument
4878 IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, SDLoc dl) argument
5297 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) argument
5882 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) argument
5911 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) argument
6298 DebugLoc dl = MI->getDebugLoc(); local
6413 DebugLoc dl = MI->getDebugLoc(); local
6863 emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) argument
6895 emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) argument
6938 DebugLoc dl = MI->getDebugLoc(); local
7230 DebugLoc dl = MI->getDebugLoc(); local
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1291 // FIXME dl should come from parent load or store, not from address
1292 SDLoc dl(N);
1363 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1600 SDLoc dl(GA);
1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1614 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1615 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1620 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrV
2173 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2194 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2431 LowerFormalArguments_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2706 LowerFormalArguments_Darwin( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3156 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs, SmallVectorImpl<SDValue> &MemOpChains, SDLoc dl) argument
3174 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, bool isPPC64, bool isDarwinABI, SDLoc dl) argument
3267 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) argument
3279 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, SDLoc dl) argument
3304 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) argument
3331 PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall, SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass, SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys, const PPCSubtarget &Subtarget) argument
3518 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3564 FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const argument
3670 SDLoc &dl = CLI.DL; local
3705 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3942 LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4357 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4760 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
5430 BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, SDLoc dl) argument
5456 BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, SDLoc dl, EVT DestVT = MVT::Other) argument
5466 BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl, EVT DestVT = MVT::Other) argument
5476 BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, SDLoc dl, EVT DestVT = MVT::Other) argument
5487 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, SDLoc dl) argument
5681 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) argument
6270 DebugLoc dl = MI->getDebugLoc(); local
6338 DebugLoc dl = MI->getDebugLoc(); local
6728 DebugLoc dl = MI->getDebugLoc(); local
6756 DebugLoc dl = MI->getDebugLoc(); local
6871 DebugLoc dl = MI->getDebugLoc(); local
6941 DebugLoc dl = MI->getDebugLoc(); local
7084 DebugLoc dl = MI->getDebugLoc(); local
7116 DebugLoc dl = MI->getDebugLoc(); local
[all...]
/external/qemu-pc-bios/bochs/bios/
H A Drombios.c789 Bit8u bl, bh, dl, dh, cl, ch, al, ah; member in struct:__anon30272::__anon30273::__anon30275
808 Bit8u dl, dh; member in struct:__anon30276::__anon30277::__anon30280
4361 regs.u.r8.dl = mouse_data3;
4646 regs.u.r8.dl = inb_cmos(0x34);
6066 /* basic checks : emulation should be active, dl should equal the emulated drive */
6249 outLBA(cylinder,hd_heads,head,hd_sectors,sector,dl)
6255 Bit16u dl;
6286 mov bl,14[bp] // dl
8062 mov dl, _int19_function.bootdrv + 2[bp] local
8143 ;; Set the magic number in ax and the boot drive in dl
8145 mov dl, _int19_function.bootdrv + 0[bp] local
8507 cmp al,dl ;; int13 on emulated drive local
8525 and dl,#0xE0 ;; mask to get device class, including cdroms local
8526 cmp al,dl ;; al is 0x00 or 0x80 local
8539 dec dl ;; real drive is dl - 1 local
8575 test dl, #0x80 local
8585 cmp dl, #0xE0 local
8858 mov dl, al ;; DL = sectors local
9002 mov dl, al ;; DL = sectors local
[all...]
/external/chromium_org/third_party/dom_distiller_js/package/js/
H A Ddomdistiller.js71 function dl(a){return new bl[a]}
480 function cl(a,b,c){var d=bl[a];if(d&&!d.cZ){_=d.prototype}else{!d&&(d=bl[a]=function(){});_=d.prototype=b<0?{}:dl(b);_.cM=c}for(var e=3;e<arguments.length;++e){arguments[e].prototype=_}if(d.cZ){_.cZ=d.cZ;d.cZ=null}}
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/
H A Dorg.mortbay.jetty.util_6.1.23.v201004211559.jarMETA-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ...
H A Dcom.ibm.icu_4.2.1.v20100412.jarMETA-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ...

Completed in 442 milliseconds

123456