/external/chromium_org/v8/src/compiler/arm64/ |
H A D | instruction-codes-arm64.h | 98 // MRI = [register + immediate] 101 V(MRI) /* [%r0 + K] */ \
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/external/chromium_org/v8/src/compiler/x64/ |
H A D | instruction-codes-x64.h | 87 // MRI = [register + immediate] 91 V(MRI) /* [%r1 + K] */ \
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/external/llvm/lib/CodeGen/ |
H A D | MachineTraceMetrics.cpp | 42 MRI(nullptr), Loops(nullptr) { 57 MRI = &MF->getRegInfo(); 624 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp) 627 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg); 640 const MachineRegisterInfo *MRI) { 654 Deps.push_back(DataDep(MRI, Reg, MO.getOperandNo())); 665 const MachineRegisterInfo *MRI) { 673 Deps.push_back(DataDep(MRI, Reg, i)); 769 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); 834 getPHIDeps(&UseMI, Deps, TBI.Pred, MTM.MRI); [all...] |
H A D | LiveVariables.cpp | 133 assert(MRI->getVRegDef(reg) && "Register use before def!"); 168 if (MBB == MRI->getVRegDef(reg)->getParent()) return; 179 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI); 502 MRI = &mf.getRegInfo(); 516 if (!MRI->isSSA()) 588 else if (!MRI->isReserved(MOReg)) 601 else if (!MRI->isReserved(MOReg)) 617 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(), 653 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) 717 MachineRegisterInfo &MRI) { 715 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument [all...] |
H A D | TargetRegisterInfo.cpp | 269 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 270 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 285 if (MRI.isReserved(Phys))
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H A D | RegisterScavenging.cpp | 76 MRI = &MF.getRegInfo(); 83 assert(MRI->tracksLiveness() && 238 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && 254 used |= MRI->getReservedRegs(); 256 used.reset(MRI->getReservedRegs());
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H A D | EarlyIfConversion.cpp | 84 MachineRegisterInfo *MRI; member in class:__anon25739::SSAIfConv 158 MRI = &MF.getRegInfo(); 245 MachineInstr *DefMI = MRI->getVRegDef(Reg); 484 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst)); 584 MachineRegisterInfo *MRI; member in class:__anon25740::EarlyIfConverter 789 MRI = &MF.getRegInfo();
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H A D | MachineVerifier.cpp | 70 const MachineRegisterInfo *MRI; member in struct:__anon25778::MachineVerifier 189 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); 297 MRI = &MF.getRegInfo(); 456 regsReserved = MRI->getReservedRegs(); 486 MRI->verifyUseLists(); 505 if (MRI->isSSA()) { 862 if (MRI->tracksLiveness() && !MI->isDebugValue()) 889 if (!MRI->isSSA() && MO->isUse() && 913 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 1053 } else if (MRI [all...] |
/external/llvm/lib/Object/ |
H A D | IRObjectFile.cpp | 55 std::unique_ptr<MCRegisterInfo> MRI(T->createMCRegInfo(Triple)); 56 if (!MRI) 59 std::unique_ptr<MCAsmInfo> MAI(T->createMCAsmInfo(*MRI, Triple)); 73 MCContext MCCtx(MAI.get(), MRI.get(), &MOFI);
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUAsmBackend.cpp | 99 const MCRegisterInfo &MRI, 98 createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 292 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) { argument 294 const MachineInstr *DefMI = MRI.getVRegDef(VReg); 305 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, argument 307 VReg = removeCopies(MRI, VReg); 311 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); 312 const MachineInstr *DefMI = MRI.getVRegDef(VReg); 335 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); 352 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); 374 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 376 RI.getCommonSubClass(MRI 415 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 669 MachineRegisterInfo *MRI = &MF->getRegInfo(); local [all...] |
H A D | AArch64FrameLowering.cpp | 160 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 194 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 766 MachineRegisterInfo *MRI = &MF.getRegInfo(); local 772 MRI->setPhysRegUsed(AArch64::FP); 773 MRI->setPhysRegUsed(AArch64::LR); 779 MRI->setPhysRegUsed(RegInfo->getBaseRegister()); 801 const bool OddRegUsed = MRI->isPhysRegUsed(OddReg); 802 const bool EvenRegUsed = MRI->isPhysRegUsed(EvenReg); 823 MRI->setPhysRegUsed(Reg); 877 MRI [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_debug.cpp | 236 OwningPtr<const MCRegisterInfo> MRI(T->createMCRegInfo(Triple)); 237 if (!MRI) { 251 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
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/external/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 553 const MCRegisterInfo *MRI = nullptr) const { 556 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
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H A D | MCContext.h | 62 const MCRegisterInfo *MRI; member in class:llvm::MCContext 179 explicit MCContext(const MCAsmInfo *MAI, const MCRegisterInfo *MRI, 188 const MCRegisterInfo *getRegisterInfo() const { return MRI; }
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 38 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); 40 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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/external/mesa3d/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_debug.cpp | 236 OwningPtr<const MCRegisterInfo> MRI(T->createMCRegInfo(Triple)); 237 if (!MRI) { 251 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 165 const MCRegisterInfo *MRI = Context.getRegisterInfo(); local 400 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI))); 421 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset)); 428 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 453 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 484 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 1357 MachineRegisterInfo &MRI = MF.getRegInfo(); 1360 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills)) 1393 MachineRegisterInfo &MRI = MF.getRegInfo(); local 1403 MRI 1747 const MCRegisterInfo *MRI = Context.getRegisterInfo(); local [all...] |
H A D | Thumb1FrameLowering.cpp | 44 const Thumb1RegisterInfo &MRI, 47 MRI, MIFlags); 91 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local 224 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI))); 242 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset)); 248 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 41 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 37 const MCRegisterInfo &MRI, 39 : MCInstPrinter(MAI, MII, MRI) { 46 const MCRegisterInfo &MRI, 48 : AArch64InstPrinter(MAI, MII, MRI, STI) {} 1163 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || 1164 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) 1166 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || 1167 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) 1169 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || 1170 MRI 35 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 44 AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 317 MachineRegisterInfo &MRI = MF.getRegInfo(); local 319 if (!MRI.isLiveIn(Reg)) { 320 VirtualRegister = MRI.createVirtualRegister(RC); 321 MRI.addLiveIn(Reg, VirtualRegister); 323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 271 const MachineRegisterInfo *MRI = nullptr) const; 793 const MachineRegisterInfo *MRI) const { 805 const MachineRegisterInfo *MRI, 813 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 818 unsigned Reg, MachineRegisterInfo *MRI) const { 891 const MachineRegisterInfo *MRI, 804 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const argument 890 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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/external/llvm/tools/llvm-rtdyld/ |
H A D | llvm-rtdyld.cpp | 327 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); 328 assert(MRI && "Unable to create target register info!"); 330 std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName)); 333 MCContext Ctx(MAI.get(), MRI.get(), nullptr); 342 TheTarget->createMCInstPrinter(0, *MAI, *MII, *MRI, *STI));
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 317 MachineRegisterInfo &MRI = MF.getRegInfo(); local 319 if (!MRI.isLiveIn(Reg)) { 320 VirtualRegister = MRI.createVirtualRegister(RC); 321 MRI.addLiveIn(Reg, VirtualRegister); 323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 85 const MachineRegisterInfo *MRI; member in struct:__anon26019::HexagonPeephole 118 MRI = &MF.getRegInfo(); 250 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
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