/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 421 const MCRegisterInfo &MRI, 428 const MCRegisterInfo &MRI, 420 createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument 427 createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 505 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local 732 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 740 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 748 unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 764 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 795 nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8)); 803 nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 1063 MachineRegisterInfo &MRI = MF.getRegInfo(); local 1064 MRI.setPhysRegUnused(LR); 1101 (MRI [all...] |
H A D | PPCInstrInfo.cpp | 121 const MachineRegisterInfo *MRI = local 123 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || 124 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); 600 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 602 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 636 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 638 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 673 if (MRI 1619 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 1889 IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, MachineRegisterInfo &MRI) argument 1900 IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) argument 1904 IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) argument 1908 IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) argument 1916 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 419 const MachineRegisterInfo *MRI) { 422 return MRI->getUniqueVRegDef(Reg); 433 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) { argument 434 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg())) 443 const MachineRegisterInfo *MRI, 446 MachineInstr *RLL = getDef(SrcReg, MRI); 449 RLL = getDef(LGFR->getOperand(1).getReg(), MRI); 454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); 458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI); 474 eraseIfDead(LGFR, MRI); 418 getDef(unsigned Reg, const MachineRegisterInfo *MRI) argument 442 removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI) argument 679 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local [all...] |
H A D | SystemZISelLowering.cpp | 673 MachineRegisterInfo &MRI = MF.getRegInfo(); local 716 unsigned VReg = MRI.createVirtualRegister(RC); 717 MRI.addLiveIn(VA.getLocReg(), VReg); 2604 MachineRegisterInfo &MRI = MF.getRegInfo(); local 2606 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass); 2736 MachineRegisterInfo &MRI = MF.getRegInfo(); local 2764 unsigned OrigVal = MRI.createVirtualRegister(RC); 2765 unsigned OldVal = MRI.createVirtualRegister(RC); 2767 MRI.createVirtualRegister(RC) : Src2.getReg()); 2768 unsigned RotatedOldVal = (IsSubWord ? MRI 2860 MachineRegisterInfo &MRI = MF.getRegInfo(); local 2972 MachineRegisterInfo &MRI = MF.getRegInfo(); local 3089 MachineRegisterInfo &MRI = MF.getRegInfo(); local 3121 MachineRegisterInfo &MRI = MF.getRegInfo(); local 3291 MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | IfConversion.cpp | 165 MachineRegisterInfo *MRI; member in class:__anon25750::IfConverter 276 MRI = &MF.getRegInfo(); 284 PreRegAlloc = MRI->isSSA();
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H A D | MachineInstr.cpp | 57 MachineRegisterInfo &MRI = MF->getRegInfo(); local 58 MRI.removeRegOperandFromUseList(this); 60 MRI.addRegOperandToUseList(this); 95 // MRI may keep uses and defs in different list positions. 99 MachineRegisterInfo &MRI = MF->getRegInfo(); local 100 MRI.removeRegOperandFromUseList(this); 102 MRI.addRegOperandToUseList(this); 595 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { argument 598 MRI.removeRegOperandFromUseList(&Operands[i]); 604 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { argument 620 moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI) argument 677 MachineRegisterInfo *MRI = getRegInfo(); local 1463 const MachineRegisterInfo *MRI = nullptr; local 1545 const MachineRegisterInfo &MRI = MF->getRegInfo(); local [all...] |
H A D | MachineVerifier.cpp | 70 const MachineRegisterInfo *MRI; member in struct:__anon25778::MachineVerifier 189 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); 297 MRI = &MF.getRegInfo(); 456 regsReserved = MRI->getReservedRegs(); 486 MRI->verifyUseLists(); 505 if (MRI->isSSA()) { 862 if (MRI->tracksLiveness() && !MI->isDebugValue()) 889 if (!MRI->isSSA() && MO->isUse() && 913 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 1053 } else if (MRI [all...] |
H A D | RegisterCoalescer.cpp | 80 MachineRegisterInfo* MRI; member in class:__anon25794::RegisterCoalescer 271 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local 283 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); 285 } else if (!MRI.getRegClass(Src)->contains(Dst)) { 290 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 291 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 624 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) { 647 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) 668 for (MachineRegisterInfo::use_iterator UI = MRI [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGISel.cpp | 553 MachineRegisterInfo &MRI = MF->getRegInfo(); local 569 MRI.constrainRegClass(To, MRI.getRegClass(From)); 571 MRI.replaceRegWith(From, To); 577 MRI.freezeReservedRegs(*MF);
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/external/llvm/lib/MC/ |
H A D | MCAsmStreamer.cpp | 945 const MCRegisterInfo *MRI = getContext().getRegisterInfo(); local 946 unsigned LLVMRegister = MRI->getLLVMRegNum(Register, true);
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H A D | MCDwarf.cpp | 1339 const MCRegisterInfo *MRI = context.getRegisterInfo(); local 1394 assert(MRI->getRARegister() <= 255 && 1396 streamer.EmitIntValue(MRI->getDwarfRegNum(MRI->getRARegister(), true), 1); 1399 MRI->getDwarfRegNum(MRI->getRARegister(), true));
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 165 const MCRegisterInfo *MRI = Context.getRegisterInfo(); local 400 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI))); 421 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset)); 428 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 453 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 484 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 1357 MachineRegisterInfo &MRI = MF.getRegInfo(); 1360 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills)) 1393 MachineRegisterInfo &MRI = MF.getRegInfo(); local 1403 MRI 1747 const MCRegisterInfo *MRI = Context.getRegisterInfo(); local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 1770 MachineRegisterInfo *MRI; member in struct:__anon25981::ARMPreAllocLoadStoreOpt 1800 MRI = &Fn.getRegInfo(); 2051 MRI->constrainRegClass(EvenReg, TRC); 2052 MRI->constrainRegClass(OddReg, TRC); 2088 MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg); 2089 MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg);
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H A D | ARMISelDAGToDAG.cpp | 3368 MachineRegisterInfo &MRI = MF->getRegInfo(); local 3375 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); 3412 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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H A D | ARMBaseInstrInfo.cpp | 1335 const MachineRegisterInfo *MRI) const { 1393 if (!MRI || 1399 MachineInstr *Def0 = MRI->getVRegDef(Addr0); 1400 MachineInstr *Def1 = MRI->getVRegDef(Addr1); 1403 if (!produceSameValue(Def0, Def1, MRI)) 1684 const MachineRegisterInfo &MRI, 1688 if (!MRI.hasOneNonDBGUse(Reg)) 1690 MachineInstr *MI = MRI.getVRegDef(Reg); 1745 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local 1746 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, thi 1683 canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII) argument 3891 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
H A D | ARMISelLowering.cpp | 1848 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1856 MachineInstr *Def = MRI->getVRegDef(VR); 1997 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 2025 MFI, MRI, TII)) 6300 MachineRegisterInfo *MRI = &MF->getRegInfo(); local 6334 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6339 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 6344 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 6361 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6365 unsigned NewVReg2 = MRI 1847 MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument 6415 MachineRegisterInfo *MRI = &MF->getRegInfo(); local 6941 MachineRegisterInfo &MRI = MF->getRegInfo(); local 7202 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 7423 MachineRegisterInfo &MRI = Fn->getRegInfo(); local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 65 MachineRegisterInfo *MRI; member in struct:__anon26012::HexagonHardwareLoops 302 MRI = &MF.getRegInfo(); 355 MachineInstr *DI = MRI->getVRegDef(PhiOpReg); 363 if (MRI->getVRegDef(IndReg) == Phi) { 382 MachineInstr *PredI = MRI->getVRegDef(PredR); 418 IVOp = MRI->getVRegDef(F->first); 469 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); 501 MachineInstr *CondI = MRI->getVRegDef(PredReg); 593 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); 596 OldInsts.push_back(MRI [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 189 MachineRegisterInfo &MRI = MF->getRegInfo(); local 202 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg())) 244 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister); 279 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 280 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 380 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 381 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 633 MachineRegisterInfo &MRI = MF.getRegInfo(); local 634 MRI.addLiveIn(Reg); 654 MachineRegisterInfo &MRI local [all...] |
H A D | SIISelLowering.cpp | 291 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); local 295 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64); 463 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); local 471 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass); 472 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass); 473 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 474 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 509 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); local 510 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); 521 MachineRegisterInfo &MRI local 536 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); local 1272 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); local 1673 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local [all...] |
H A D | SIInstrInfo.cpp | 193 MachineRegisterInfo &MRI = MF->getRegInfo(); local 203 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF); 218 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs); 371 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local 377 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg()))) 736 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local 740 return MRI.getRegClass(MI.getOperand(OpNo).getReg()); 761 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local 772 unsigned Reg = MRI.createVirtualRegister(VRC); 779 MachineRegisterInfo &MRI, 778 buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const argument 804 buildExtractSubRegOrImm( MachineBasicBlock::iterator MII, MachineRegisterInfo &MRI, MachineOperand &Op, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const argument 826 split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist, MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineOperand &Op) const argument 857 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local 1180 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 1371 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 1423 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 1485 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local [all...] |
H A D | AMDGPUISelLowering.cpp | 2094 MachineRegisterInfo &MRI = MF.getRegInfo(); local 2096 if (!MRI.isLiveIn(Reg)) { 2097 VirtualRegister = MRI.createVirtualRegister(RC); 2098 MRI.addLiveIn(Reg, VirtualRegister); 2100 VirtualRegister = MRI.getLiveInVirtReg(Reg);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 2965 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 2989 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg)); 2992 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC); 3017 unsigned ValReg = MRI.createVirtualRegister(ValueRC); 3019 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg); 3039 UpdReg = MRI.createVirtualRegister(ValueRC);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1633 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { argument 1638 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), 1639 E = MRI.def_instr_end(); I != E; ++I) { 1697 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 1698 return regIsPICBase(BaseReg, MRI); 1717 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 1718 return regIsPICBase(BaseReg, MRI); 2985 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 2987 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI 3012 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 3872 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const argument 5390 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
H A D | X86ISelLowering.cpp | 3089 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 3097 MachineInstr *Def = MRI->getVRegDef(VR); 3293 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 3304 MFI, MRI, TII)) 13172 MachineRegisterInfo &MRI = MF.getRegInfo(); 13188 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 17077 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 17134 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 17135 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 17165 OffsetReg = MRI 3088 MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const X86InstrInfo *TII) argument [all...] |