Searched refs:MI (Results 151 - 175 of 514) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp84 // DistanceMap - Keep track the distance of a MI from the start of the
101 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
107 MachineInstr *MI, unsigned Dist);
118 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
134 void processCopy(MachineInstr *MI);
138 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
139 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
173 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
180 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, argument
188 if (!MI
320 MachineInstr *MI = MO.getParent(); local
338 isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys) argument
359 isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS) argument
401 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument
434 isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) argument
507 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC, MachineInstr *MI, unsigned Dist) argument
576 MachineInstr *MI = mi; local
717 processCopy(MachineInstr *MI) argument
914 isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI) argument
1296 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) argument
1336 processTiedPairs(MachineInstr *MI, TiedPairList &TiedPairs, unsigned &Dist) argument
1629 MachineInstr *MI = MBBI; local
[all...]
H A DLocalStackSlotAllocation.cpp50 MachineBasicBlock::iterator MI; // Instr referencing the frame member in class:__anon25757::FrameRef
55 MI(I), LocalOffset(Offset), FrameIdx(Idx) {}
59 MachineBasicBlock::iterator getMachineInstr() const { return MI; }
257 const MachineInstr *MI,
262 return TRI->isFrameOffsetLegal(MI, Offset);
288 MachineInstr *MI = I; local
292 if (MI->isDebugValue() ||
293 MI->getOpcode() == TargetOpcode::STACKMAP ||
294 MI->getOpcode() == TargetOpcode::PATCHPOINT)
303 for (unsigned i = 0, e = MI
254 lookupCandidateBaseReg(int64_t BaseOffset, int64_t FrameSizeAdjust, int64_t LocalFrameOffset, const MachineInstr *MI, const TargetRegisterInfo *TRI) argument
334 MachineInstr *MI = I; local
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H A DPeepholeOptimizer.cpp130 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
131 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
133 bool optimizeSelect(MachineInstr *MI);
134 bool optimizeCopyOrBitcast(MachineInstr *MI);
135 bool isMoveImmediate(MachineInstr *MI,
138 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
141 bool isLoadFoldable(MachineInstr *MI,
204 /// \brief Create a ValueTracker instance for the value defines by \p MI
207 /// track. It does not need to match the sub register index used in \p MI.
212 ValueTracker(const MachineInstr &MI, unsigne argument
263 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, SmallPtrSet<MachineInstr*, 8> &LocalMIs) argument
413 optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB) argument
434 optimizeSelect(MachineInstr *MI) argument
531 optimizeCopyOrBitcast(MachineInstr *MI) argument
601 isLoadFoldable( MachineInstr *MI, SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) argument
623 isMoveImmediate(MachineInstr *MI, SmallSet<unsigned, 4> &ImmDefRegs, DenseMap<unsigned, MachineInstr*> &ImmDefMIs) argument
644 foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB, SmallSet<unsigned, 4> &ImmDefRegs, DenseMap<unsigned, MachineInstr*> &ImmDefMIs) argument
694 MachineInstr *MI = &*MII; local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp215 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI, argument
217 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
218 assert(i < MI->getNumOperands() &&
230 if (!MI->mayLoad() && !MI->mayStore())
238 MachineFunction &MF = *MI->getParent()->getParent();
260 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, FPOffset))
268 if (isFrameOffsetLegal(MI, Offset))
275 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, argument
278 assert(MI
306 resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const argument
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H A DAArch64ExpandPseudoInsts.cpp87 static bool tryOrrMovk(uint64_t UImm, uint64_t OrrImm, MachineInstr &MI, argument
98 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
99 .addOperand(MI.getOperand(0))
105 const unsigned DstReg = MI.getOperand(0).getReg();
106 const bool DstIsDead = MI.getOperand(0).isDead();
108 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
114 transferImpOps(MI, MIB, MIB1);
115 MI.eraseFromParent();
138 static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
165 BuildMI(MBB, MBBI, MI
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H A DAArch64StorePairSuppress.cpp51 bool isNarrowFPStore(const MachineInstr &MI);
107 bool AArch64StorePairSuppress::isNarrowFPStore(const MachineInstr &MI) { argument
108 switch (MI.getOpcode()) {
145 for (auto &MI : MBB) {
146 if (!isNarrowFPStore(MI))
150 if (TII->getLdStBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
153 if (!SuppressSTP && shouldAddSTPToBlock(MI.getParent()))
156 DEBUG(dbgs() << "Unpairing store " << MI << "\n");
158 TII->suppressLdStPair(&MI);
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp50 bool isIndirectJump(const MCInst &MI) { argument
51 if (MI.getOpcode() == Mips::JALR) {
54 assert(MI.getOperand(0).isReg());
55 return MI.getOperand(0).getReg() == Mips::ZERO;
57 return MI.getOpcode() == Mips::JR;
60 bool isStackPointerFirstOperand(const MCInst &MI) { argument
61 return (MI.getNumOperands() > 0 && MI.getOperand(0).isReg()
62 && MI.getOperand(0).getReg() == Mips::SP);
65 bool isCall(const MCInst &MI, boo argument
105 sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) argument
116 sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, const MCSubtargetInfo &STI, bool MaskBefore, bool MaskAfter) argument
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/external/llvm/lib/Target/Mips/
H A DMipsMCInstLower.cpp165 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const { argument
169 OutMI.addOperand(LowerOperand(MI->getOperand(0)));
172 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
173 MI->getOperand(2).getMBB(),
178 lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode, argument
184 const MachineOperand &MO = MI->getOperand(I);
189 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
190 MI->getOperand(3).getMBB(), Kind));
193 bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI, argument
195 switch (MI
219 Lower(const MachineInstr *MI, MCInst &OutMI) const argument
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H A DMipsDelaySlotFiller.cpp73 void init(const MachineInstr &MI);
76 void setCallerSaved(const MachineInstr &MI);
86 bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
106 /// Return true if MI cannot be moved to delay slot.
107 bool hasHazard(const MachineInstr &MI);
120 virtual bool hasHazard_(const MachineInstr &MI) = 0;
128 bool hasHazard_(const MachineInstr &MI) override { return true; }
136 bool hasHazard_(const MachineInstr &MI) override;
148 bool hasHazard_(const MachineInstr &MI) override;
155 /// Get the list of underlying objects of MI'
249 hasUnoccupiedSlot(const MachineInstr *MI) argument
292 init(const MachineInstr &MI) argument
309 setCallerSaved(const MachineInstr &MI) argument
348 update(const MachineInstr &MI, unsigned Begin, unsigned End) argument
386 hasHazard(const MachineInstr &MI) argument
408 hasHazard_(const MachineInstr &MI) argument
429 hasHazard_(const MachineInstr &MI) argument
461 getUnderlyingObjects(const MachineInstr &MI, SmallVectorImpl<ValueType> &Objects) const argument
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H A DMipsSEInstrInfo.h36 unsigned isLoadFromStackSlot(const MachineInstr *MI,
44 unsigned isStoreToStackSlot(const MachineInstr *MI,
48 MachineBasicBlock::iterator MI, DebugLoc DL,
53 MachineBasicBlock::iterator MI,
60 MachineBasicBlock::iterator MI,
66 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
/external/llvm/lib/Target/NVPTX/
H A DNVPTXutil.cpp21 bool isParamLoad(const MachineInstr *MI) { argument
22 if ((MI->getOpcode() != NVPTX::LD_i32_avar) &&
23 (MI->getOpcode() != NVPTX::LD_i64_avar))
25 if (MI->getOperand(2).isImm() == false)
27 if (MI->getOperand(2).getImm() != NVPTX::PTXLdStInstCode::PARAM)
H A DNVPTXRegisterInfo.cpp97 MachineInstr &MI = *II; local
98 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
100 MachineFunction &MF = *MI.getParent()->getParent();
102 MI.getOperand(FIOperandNum + 1).getImm();
105 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
106 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.h42 unsigned isLoadFromStackSlot(const MachineInstr *MI,
50 unsigned isStoreToStackSlot(const MachineInstr *MI,
71 MachineBasicBlock::iterator MI,
77 MachineBasicBlock::iterator MI,
88 MachineBasicBlock::iterator MI,
/external/llvm/lib/Target/R600/
H A DR600InstrInfo.cpp40 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
41 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
44 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
50 MachineBasicBlock::iterator MI, DebugLoc DL,
69 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
76 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
167 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
168 if (isALUInstr(MI->getOpcode()))
170 if (isVector(*MI) || isCubeO
49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp134 MachineInstr *MI = MBBI;
135 MachineFunction &MF = *MI->getParent()->getParent();
136 uint64_t TSFlags = MI->getDesc().TSFlags;
149 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
156 const MCInstrDesc &MCID = MI->getDesc();
158 bool isLoad = !MI->mayStore();
159 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
160 const MachineOperand &Base = MI->getOperand(2);
161 const MachineOperand &Offset = MI
458 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument
506 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument
543 IsCPSRDead(MachineInstr *MI) argument
932 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
980 isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const argument
1123 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
1171 isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const argument
1298 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); local
1319 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF); local
1539 isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const argument
1634 getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) argument
1659 commuteInstruction(MachineInstr *MI, bool NewMI) const argument
1720 analyzeSelect(const MachineInstr *MI, SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const argument
1741 optimizeSelect(MachineInstr *MI, bool PreferFalse) const argument
1885 tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes) argument
1996 rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII) argument
2141 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
2175 isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, int CmpMask, bool CommonUse) argument
2259 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); local
2606 getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, const MachineInstr *MI) argument
3261 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
3284 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
3822 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument
3927 verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const argument
4033 getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr *MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) argument
4062 setExecutionDomain(MachineInstr *MI, unsigned Domain) const argument
4268 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
4330 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
[all...]
H A DARMAsmPrinter.cpp126 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
128 const MachineOperand &MO = MI->getOperand(OpNum);
138 const MachineFunction &MF = *MI->getParent()->getParent();
201 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
211 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
213 if (MI->getOperand(OpNum).isReg()) {
215 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
221 if (!MI->getOperand(OpNum).isImm())
223 O << MI->getOperand(OpNum).getImm();
227 printOperand(MI, OpNu
376 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
897 EmitJumpTable(const MachineInstr *MI) argument
948 EmitJump2Table(const MachineInstr *MI) argument
1009 EmitUnwindingInstruction(const MachineInstr *MI) argument
1153 EmitInstruction(const MachineInstr *MI) argument
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H A DThumb1FrameLowering.h34 MachineBasicBlock::iterator MI,
38 MachineBasicBlock::iterator MI,
47 MachineBasicBlock::iterator MI) const override;
H A DARMBaseInstrInfo.h75 bool isPredicated(const MachineInstr *MI) const override;
77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78 int PIdx = MI->findFirstPredOperandIdx();
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
83 bool PredicateInstruction(MachineInstr *MI,
89 bool DefinesPredicate(MachineInstr *MI,
92 bool isPredicable(MachineInstr *MI) const override;
96 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
98 unsigned isLoadFromStackSlot(const MachineInstr *MI,
100 unsigned isStoreToStackSlot(const MachineInstr *MI,
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp66 MachineInstr * MI, MachineBasicBlock * BB) const
70 MachineBasicBlock::iterator I = MI;
72 if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) {
73 AppendS_WAITCNT(MI, *BB, llvm::next(I));
77 switch (MI->getOpcode()) {
79 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI
65 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument
142 AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I) const argument
149 LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
181 LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const argument
203 LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
235 LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp66 MachineInstr * MI, MachineBasicBlock * BB) const
70 MachineBasicBlock::iterator I = MI;
72 if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) {
73 AppendS_WAITCNT(MI, *BB, llvm::next(I));
77 switch (MI->getOpcode()) {
79 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI
65 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument
142 AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I) const argument
149 LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
181 LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const argument
203 LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
235 LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp159 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument
162 switch (MI.getOpcode()) {
166 SrcReg = MI.getOperand(1).getReg();
167 DstReg = MI.getOperand(0).getReg();
173 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument
176 switch (MI->getOpcode()) {
189 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
190 MI->getOperand(2).isFI()) {
191 FrameIndex = MI
199 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
228 commuteInstruction(MachineInstr *MI, bool NewMI) const argument
302 findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const argument
624 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, unsigned DestReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
850 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
945 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
1105 PredicateInstruction( MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument
1230 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument
1281 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
1338 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); local
1622 MachineInstr *MI = I; local
1919 MachineInstr *MI = I; local
2036 MachineInstr *MI = I; local
[all...]
/external/llvm/lib/Target/R600/MCTargetDesc/
H A DSIMCCodeEmitter.cpp57 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
62 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
129 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, argument
133 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
134 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
145 for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
152 const MCOperand &Op = MI.getOperand(i);
172 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, argument
182 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
188 for (unsigned e = MI
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/external/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.h38 void EmitInstruction(const MachineInstr *MI) override;
40 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
43 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
H A DSystemZInstrBuilder.h28 MachineInstr *MI = MIB; local
29 MachineFunction &MF = *MI->getParent()->getParent();
31 const MCInstrDesc &MCID = MI->getDesc();
/external/llvm/lib/Target/X86/
H A DX86AsmPrinter.h44 void EmitInstruction(const MachineInstr *MI) override;
46 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
49 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,

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