Searched refs:TII (Results 151 - 175 of 224) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h33 const TargetInstrInfo *TII; member in class:llvm::RegScavenger
H A DResourcePriorityQueue.h62 const TargetInstrInfo *TII; member in class:llvm::ResourcePriorityQueue
H A DVirtRegMap.h42 const TargetInstrInfo *TII; member in class:llvm::VirtRegMap
H A DMachineInstr.h890 const TargetInstrInfo *TII,
907 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
921 const TargetInstrInfo *TII,
1008 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
1141 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
/external/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h120 const TargetInstrInfo *TII; member in class:llvm::AggressiveAntiDepBreaker
H A DBranchFolding.h90 const TargetInstrInfo *TII; member in class:llvm::BranchFolder
H A DLiveDebugVariables.cpp133 LiveIntervals &LIS, const TargetInstrInfo &TII);
932 const TargetInstrInfo &TII) {
938 BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE),
941 BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
946 const TargetInstrInfo &TII) {
958 insertDebugValue(MBB, Start, LocNo, LIS, TII);
968 insertDebugValue(MBB, Start, LocNo, LIS, TII);
982 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); local
986 userValues[i]->emitDebugValues(VRM, *LIS, *TII);
929 insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
945 emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
H A DMachineBlockPlacement.cpp185 const TargetInstrInfo *TII; member in class:__anon25760::MachineBlockPlacement
888 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough())
992 if (!TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) {
1009 if (TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) {
1019 !TII->ReverseBranchCondition(Cond)) {
1025 TII->RemoveBranch(*PrevBB);
1026 TII->InsertBranch(*PrevBB, FBB, TBB, Cond, dl);
1037 if (!TII->AnalyzeBranch(F.back(), TBB, FBB, Cond))
1114 TII = F.getTarget().getInstrInfo();
H A DMachineRegisterInfo.cpp70 const TargetInstrInfo *TII = TM.getInstrInfo(); local
84 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
366 const TargetInstrInfo &TII) {
381 TII.get(TargetOpcode::COPY), LiveIns[i].second)
364 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
H A DPrologEpilogInserter.cpp188 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local
196 int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
197 int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
340 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local
356 TII.storeRegToStackSlot(*EntryBlock, I, Reg, true, CSI[i].getFrameIdx(),
384 TII.loadRegFromStackSlot(*MBB, I, Reg, CSI[i].getFrameIdx(), RC, TRI);
743 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local
748 int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
749 int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
H A DRegisterScavenging.cpp74 TII = TM.getInstrInfo();
124 bool isPred = TII->isPredicated(MI);
417 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
425 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
H A DVirtRegMap.cpp57 TII = mf.getTarget().getInstrInfo();
160 const TargetInstrInfo *TII; member in class:__anon25833::VirtRegRewriter
209 TII = TM->getInstrInfo();
400 MI->setDesc(TII->get(TargetOpcode::KILL));
H A DSplitKit.h48 const TargetInstrInfo &TII; member in class:llvm::SplitAnalysis
217 const TargetInstrInfo &TII; member in class:llvm::SplitEditor
H A DMachineCSE.cpp42 const TargetInstrInfo *TII; member in class:__anon25762::MachineCSE
383 if (TII->isAsCheapAsAMove(MI)) {
470 MachineInstr *NewMI = TII->commuteInstruction(MI);
480 (void)TII->commuteInstruction(MI);
666 TII = MF.getTarget().getInstrInfo();
H A DPHIElimination.cpp243 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); local
248 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
264 TII->get(TargetOpcode::COPY), DestReg)
388 TII->get(TargetOpcode::IMPLICIT_DEF),
397 TII->get(TargetOpcode::COPY), IncomingReg)
H A DGCStrategy.cpp71 const TargetInstrInfo *TII; member in class:__anon25748::GCMachineCodeAnalysis
349 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
406 TII = TM->getInstrInfo();
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h33 const TargetInstrInfo *TII; member in class:llvm::InstrEmitter
H A DResourcePriorityQueue.cpp48 TII = IS->getTargetLowering()->getTargetMachine().getInstrInfo();
262 if (!ResourcesModel->canReserveResources(&TII->get(
302 ResourcesModel->reserveResources(&TII->get(
450 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
553 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
H A DSelectionDAGDumper.cpp39 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo())
40 if (getMachineOpcode() < TII->getNumOpcodes())
41 return TII->getName(getMachineOpcode());
114 else if (const TargetIntrinsicInfo *TII = G->getTarget().getIntrinsicInfo())
115 return TII->getName(IID);
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp137 const Thumb2InstrInfo *TII; member in class:__anon26006::Thumb2SizeReduce
494 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
555 TII->get(ARM::tADDrSPi))
656 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
663 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
666 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
684 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
781 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
1006 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
H A DARMISelLowering.cpp1122 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
1123 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1849 const TargetInstrInfo *TII) {
1860 if (!TII->isLoadFromStackSlot(Def, FI))
1998 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
2025 MFI, MRI, TII))
6297 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
6335 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6341 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6345 BuildMI(*MBB, MI, dl, TII
1847 MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
6412 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
6863 emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) argument
6895 emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) argument
6929 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
7163 const TargetInstrInfo &TII = *TM.getInstrInfo(); local
7229 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
7499 const ARMBaseInstrInfo *TII = local
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp42 const TargetInstrInfo &TII; member in class:__anon26050::final
57 TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
98 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
102 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
H A DMipsOptimizePICCall.cpp133 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
136 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600RegisterInfo.cpp24 TII(tii)
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h171 const TargetInstrInfo *TII,
180 const AArch64InstrInfo *TII);

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