/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_pair_regalloc.c | 441 struct ra_regs * regs, 450 ra_add_reg_conflict(regs, 546 struct ra_regs * regs; local 550 regs = ra_alloc_reg_set(NULL, s->C->max_temp_regs * RC_MASK_XYZW); 572 rc_class_list[class_index].Id = ra_alloc_reg_class(regs); 590 ra_class_add_reg(regs, class.Id, reg_id); 596 add_register_conflicts(regs, s->C->max_temp_regs); 626 class_id = ra_alloc_reg_class(regs); 628 ra_class_add_reg(regs, class_id, 632 ra_set_finalize(regs); 440 add_register_conflicts( struct ra_regs * regs, unsigned int max_temp_regs) argument [all...] |
/external/oprofile/module/x86/ |
H A D | op_model_athlon.c | 87 struct pt_regs * const regs) 95 op_do_profile(cpu, instruction_pointer(regs), IRQ_ENABLED(regs), i); 85 athlon_check_ctrs(uint const cpu, struct op_msrs const * const msrs, struct pt_regs * const regs) argument
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H A D | op_model_ppro.c | 83 struct pt_regs * const regs) 90 op_do_profile(cpu, instruction_pointer(regs), IRQ_ENABLED(regs), i); 81 ppro_check_ctrs(uint const cpu, struct op_msrs const * const msrs, struct pt_regs * const regs) argument
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/external/compiler-rt/lib/sanitizer_common/ |
H A D | sanitizer_stoptheworld_linux_libcdep.cc | 433 #define REG_SP regs[EF_REG29] 443 regs_struct regs; local 445 if (internal_iserror(internal_ptrace(PTRACE_GETREGS, tid, NULL, ®s), 452 *sp = regs.REG_SP; 453 internal_memcpy(buffer, ®s, sizeof(regs));
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/external/qemu/target-arm/ |
H A D | machine.c | 11 qemu_put_be32(f, env->regs[i]); 71 u.d = env->vfp.regs[i]; 86 u.d = env->vfp.regs[i]; 95 qemu_put_be64(f, env->iwmmxt.regs[i]); 129 env->regs[i] = qemu_get_be32(f); 200 env->vfp.regs[i] = u.d; 215 env->vfp.regs[i] = u.d; 222 env->iwmmxt.regs[i] = qemu_get_be64(f);
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H A D | helper.c | 339 env->regs[13] = ldl_p(rom); 342 env->regs[15] = pc & ~1; 370 stfq_le_p(buf, env->vfp.regs[reg]); 374 /* Aliases for Q regs. */ 377 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); 378 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); 396 env->vfp.regs[reg] = ldfq_le_p(buf); 402 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); 403 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); 719 memcpy (env->fiq_regs, env->regs [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_vs.h | 103 struct brw_reg regs[PROGRAM_ADDRESS+1][128]; member in struct:brw_vs_compile
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H A D | brw_vs_emit.c | 171 * Do things as simply as possible. Allocate and populate all regs 241 /* We can only load 32 regs of push constants. */ 299 c->regs[PROGRAM_STATE_VAR][i] = stride(brw_vec4_grf(reg + i / 2, 310 /* Allocate input regs: 316 c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0); 326 /* Allocate outputs. The non-position outputs go straight into message regs. 334 assert(vert_result < Elements(c->regs[PROGRAM_OUTPUT])); 336 c->regs[PROGRAM_OUTPUT][vert_result] = brw_message_reg(slot + 1); 338 c->regs[PROGRAM_OUTPUT][vert_result] = brw_vec8_grf(reg, 0); 346 c->regs[PROGRAM_TEMPORAR [all...] |
/external/compiler-rt/lib/asan/ |
H A D | asan_linux.cc | 160 *bp = ucontext->uc_mcontext.regs[29]; 194 *pc = ucontext->uc_mcontext.regs->nip; 195 *sp = ucontext->uc_mcontext.regs->gpr[PT_R1]; 198 *bp = ucontext->uc_mcontext.regs->gpr[PT_R31];
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/external/kernel-headers/original/uapi/video/ |
H A D | uvesafb.h | 35 struct v86_regs regs; member in struct:uvesafb_task
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/external/libunwind/include/ |
H A D | libunwind-aarch64.h | 182 register uint64_t *unw_base asm ("x0") = (uint64_t*) unw_ctx->uc_mcontext.regs; \
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/external/linux-tools-perf/perf-3.12.0/tools/perf/arch/powerpc/util/ |
H A D | dwarf-regs.c | 13 #include <dwarf-regs.h>
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/external/lldb/source/Plugins/Process/Utility/ |
H A D | DynamicRegisterInfo.cpp | 78 PythonList regs (dict.GetItemForKey("registers")); 79 if (regs) 81 const uint32_t num_regs = regs.GetSize(); 94 PythonDictionary reg_info_dict(regs.GetItemAtIndex(i));
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vs.h | 103 struct brw_reg regs[PROGRAM_ADDRESS+1][128]; member in struct:brw_vs_compile
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/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_tgsi_info.c | 183 struct lp_tgsi_channel_info (*regs)[4]; 198 regs = ctx->temp; 201 regs = info->output; 247 regs[index][chan].file = TGSI_FILE_NULL; 294 regs[dst->Index][chan] = res[chan];
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/external/fonttools/Lib/fontTools/ |
H A D | afmLib.py | 118 pos = m.regs[1][1] 137 for fr, to in m.regs[1:]: 149 for fr, to in m.regs[1:]: 175 rest = rest[m.regs[0][1]:] 185 rest = rest[m.regs[0][1]:]
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/external/fonttools/Tools/fontTools/ |
H A D | afmLib.py | 118 pos = m.regs[1][1] 137 for fr, to in m.regs[1:]: 149 for fr, to in m.regs[1:]: 175 rest = rest[m.regs[0][1]:] 185 rest = rest[m.regs[0][1]:]
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/external/mesa3d/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_tgsi_info.c | 183 struct lp_tgsi_channel_info (*regs)[4]; 198 regs = ctx->temp; 201 regs = info->output; 247 regs[index][chan].file = TGSI_FILE_NULL; 294 regs[dst->Index][chan] = res[chan];
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/external/valgrind/main/coregrind/m_gdbserver/ |
H A D | valgrind-low-amd64.c | 44 static struct reg regs[] = { variable in typeref:struct:reg 123 #define max_num_regs (sizeof (regs) / sizeof (regs[0])) 163 // numbers here have to match the order of regs above. 350 regs, 367 set_register_cache (regs, dyn_num_regs);
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H A D | valgrind-low-arm.c | 40 static struct reg regs[] = { variable in typeref:struct:reg 102 #define num_regs (sizeof (regs) / sizeof (regs[0])) 191 // numbers here have to match the order of regs above 221 case 20: /* 9 "empty registers". See struct reg regs above. */ 292 regs, 304 set_register_cache (regs, num_regs);
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H A D | valgrind-low-arm64.c | 40 static struct reg regs[] = { variable in typeref:struct:reg 113 #define num_regs (sizeof (regs) / sizeof (regs[0])) 151 // numbers here have to match the order of regs above 242 regs, 254 set_register_cache (regs, num_regs);
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/external/qemu-pc-bios/bochs/bios/ |
H A D | rombios.c | 95 // - the translation policy is defined in cmos regs 0x39 & 0x3a 111 // - should handle the "don't detect" bit (cmos regs 0x3b & 0x3c) 2240 // command block & control block regs 3740 int14_function(regs, ds, iret_addr) 3741 pusha_regs_t regs; // regs pushed from PUSHA instruction 3752 addr = read_word(0x0040, (regs.u.r16.dx << 1)); 3753 timeout = read_byte(0x0040, 0x007C + regs.u.r16.dx); 3754 if ((regs.u.r16.dx < 4) && (addr > 0)) { 3755 switch (regs [all...] |
/external/qemu/target-i386/ |
H A D | helper.c | 519 env->regs[R_EDX] = env->cpuid_version; 681 env->regs[R_EAX], 682 env->regs[R_EBX], 683 env->regs[R_ECX], 684 env->regs[R_EDX], 685 env->regs[R_ESI], 686 env->regs[R_EDI], 687 env->regs[R_EBP], 688 env->regs[R_ESP], 689 env->regs[ [all...] |
/external/linux-tools-perf/perf-3.12.0/tools/perf/util/ |
H A D | unwind.c | 2 * Post mortem Dwarf CFI based unwinding on top of regs and stack dumps. 367 static int reg_value(unw_word_t *valp, struct regs_dump *regs, int id, argument 380 *valp = regs->regs[idx]; 395 if (__write || !stack || !ui->sample->user_regs.regs) { 442 if (!ui->sample->user_regs.regs) { 559 if (!data->user_regs.regs)
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/ |
H A D | r600.h | 117 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG]; member in struct:r600_pipe_state 234 state->regs[state->nregs].value = value;
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