/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 1671 unsigned Opcode = N->getOpcode(); local 1714 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1731 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1820 unsigned Opcode = N->getOpcode(); local 1829 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1830 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1850 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1851 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1860 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1861 return DAG.getNode(Opcode, D 2512 unsigned Opcode = N->getOpcode(); local [all...] |
H A D | SelectionDAG.cpp | 282 static int isSignedOp(ISD::CondCode Opcode) { argument 283 switch (Opcode) { 394 static void AddBinaryNodeIDCustom(FoldingSetNodeID &ID, unsigned Opcode, argument 396 if (isBinOpWithFlags(Opcode)) 959 BinarySDNode *SelectionDAG::GetBinarySDNode(unsigned Opcode, SDLoc DL, argument 963 if (isBinOpWithFlags(Opcode)) { 965 Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2); 974 BinarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2); 1755 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1756 return getNode(Opcode, SDLo 2647 getNode(unsigned Opcode, SDLoc DL, EVT VT) argument 2665 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue Operand) argument 2941 FoldConstantArithmetic(unsigned Opcode, EVT VT, SDNode *Cst1, SDNode *Cst2) argument 3067 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, bool nuw, bool nsw, bool exact) argument 3536 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) argument 3643 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument 3650 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument 4368 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList, ArrayRef<SDValue> Ops, MachineMemOperand *MMO, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) argument 4403 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList, ArrayRef<SDValue> Ops, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 4412 getAtomicCmpSwap( unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) argument 4439 getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) argument 4455 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value* PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 4486 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 4514 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 4540 getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef<SDValue> Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol, bool ReadMem, bool WriteMem) argument 4563 getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef<SDValue> Ops, EVT MemVT, MachineMemOperand *MMO) argument 4927 getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef<SDUse> Ops) argument 4943 getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef<SDValue> Ops) argument 5001 getNode(unsigned Opcode, SDLoc DL, ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops) argument 5006 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, ArrayRef<SDValue> Ops) argument 5084 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList) argument 5088 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1) argument 5094 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2) argument 5100 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) argument 5106 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument 5113 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument 5553 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT) argument 5559 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1) argument 5566 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument 5574 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5582 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, ArrayRef<SDValue> Ops) argument 5589 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2) argument 5595 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1) argument 5603 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5611 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5620 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, ArrayRef<SDValue> Ops) argument 5628 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument 5637 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 5646 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef<SDValue> Ops) argument 5654 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, EVT VT4, ArrayRef<SDValue> Ops) argument 5662 getMachineNode(unsigned Opcode, SDLoc dl, ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops) argument 5670 getMachineNode(unsigned Opcode, SDLoc DL, SDVTList VTs, ArrayRef<SDValue> OpsArray) argument 5736 getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef<SDValue> Ops, bool nuw, bool nsw, bool exact) argument [all...] |
H A D | DAGCombiner.cpp | 4803 unsigned Opcode = N->getOpcode(); local 4807 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND || 4808 Opcode == ISD::ANY_EXTEND) && "Expected EXTEND dag node in input!"); 4814 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode(); 4842 if (Opcode == ISD::SIGN_EXTEND) 7780 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD; local 7791 SDValue NewUse = DAG.getNode(Opcode, 10150 unsigned Opcode = ISD::DELETED_NODE; local 10161 if (Opcode [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 85 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 3576 bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 1295 unsigned Opcode = Orig->getOpcode(); local 1296 switch (Opcode) { 1308 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1336 int Opcode = MI0->getOpcode(); local 1337 if (Opcode == ARM::t2LDRpci || 1338 Opcode == ARM::t2LDRpci_pic || 1339 Opcode == ARM::tLDRpci || 1340 Opcode == ARM::tLDRpci_pic || 1341 Opcode == ARM::LDRLIT_ga_pcrel || 1342 Opcode 1999 unsigned Opcode = MI.getOpcode(); local 3880 unsigned Opcode = Node->getMachineOpcode(); local 3937 isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const argument [all...] |
H A D | ARMISelLowering.cpp | 932 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 933 switch (Opcode) { 5785 unsigned Opcode = N->getOpcode(); local 5786 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 5796 unsigned Opcode = N->getOpcode(); local 5797 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 8010 unsigned Opcode = N0.getOpcode(); local 8011 if (Opcode ! 9495 unsigned Opcode = 0; local 10553 unsigned Opcode = Op->getOpcode(); local [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 77 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 896 static const MCInstrDesc &getInstDesc(unsigned Opcode) { argument 897 return MipsInsts[Opcode]; 907 const unsigned Opcode = Inst.getOpcode(); local 910 switch (Opcode) { 1372 unsigned Opcode = Inst.getOpcode(); local 1374 if (Opcode == Mips::JALR_HB && 1381 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 121 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 122 switch (Opcode) { 2709 unsigned Opcode = 0; local 2711 Opcode = ISD::AssertSext; 2713 Opcode = ISD::AssertZext; 2714 if (Opcode) 2715 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 44 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {} 50 unsigned Opcode; member in struct:__anon26153::Comparison 55 // The mask of CC values that Opcode can produce. 1395 // a comparison of type Opcode between the AND result and CmpVal. 1562 C.Opcode = SystemZISD::TM; 1579 C.Opcode = SystemZISD::FCMP; 1583 C.Opcode = SystemZISD::ICMP; 1616 if (C.Opcode == SystemZISD::ICMP) 1619 if (C.Opcode == SystemZISD::TM) { 1625 return DAG.getNode(C.Opcode, D 1647 lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT, unsigned Extend, unsigned Opcode, SDValue Op0, SDValue Op1, SDValue &Even, SDValue &Odd) argument 2094 unsigned Opcode; local 2534 unsigned Opcode = N->getOpcode(); local [all...] |
/external/llvm/lib/Transforms/Vectorize/ |
H A D | SLPVectorizer.cpp | 152 ///\returns Opcode that can be clubbed with \p Op to create an alternate 169 ///\returns bool representing if Opcode \p Op can be part 184 unsigned Opcode = I0->getOpcode(); local 185 unsigned AltOpcode = getAltOpcode(Opcode); 188 if (!I || I->getOpcode() != ((i & 1) ? AltOpcode : Opcode)) 200 unsigned Opcode = I0->getOpcode(); local 203 if (!I || Opcode != I->getOpcode()) { 204 if (canCombineAsAltInst(Opcode) && i == 1) 209 return Opcode; 665 unsigned Opcode local 1157 unsigned Opcode = getSameOpcode(VL); local 1623 unsigned Opcode = getSameOpcode(E->Scalars); local 2800 createBinOp(IRBuilder< &Builder, unsigned Opcode, Value *L, Value *R, const Twine &Name = �) argument [all...] |
/external/mesa3d/src/gallium/include/pipe/ |
H A D | p_shader_tokens.h | 441 * Opcode is the operation code to execute. A given operation defines the 458 unsigned Opcode : 8; /* TGSI_OPCODE_ */ member in struct:tgsi_instruction
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/external/clang/include/clang/AST/ |
H A D | Expr.h | 1660 typedef UnaryOperatorKind Opcode; typedef in class:clang::StringLiteral::UnaryOperator 1668 UnaryOperator(Expr *input, Opcode opc, QualType type, 1682 Opcode getOpcode() const { return static_cast<Opcode>(Opc); } 1683 void setOpcode(Opcode O) { Opc = O; } 1693 static bool isPostfix(Opcode Op) { 1698 static bool isPrefix(Opcode Op) { 1705 static bool isIncrementOp(Opcode Op) { 1712 static bool isDecrementOp(Opcode Op) { 1719 static bool isIncrementDecrementOp(Opcode O 2914 typedef BinaryOperatorKind Opcode; typedef in class:clang::StringLiteral::OffsetOfExpr::BinaryOperator [all...] |
/external/llvm/lib/MC/MCParser/ |
H A D | AsmParser.cpp | 108 unsigned Opcode; member in struct:__anon25885::ParseStatementInfo 115 ParseStatementInfo() : Opcode(~0U), ParseError(false), AsmRewrites(nullptr) {} 117 : Opcode(~0), ParseError(false), AsmRewrites(rewrites) {} 1079 MCBinaryExpr::Opcode &Kind) { 1160 MCBinaryExpr::Opcode Kind = MCBinaryExpr::Add; 1177 MCBinaryExpr::Opcode Dummy; 1634 getTargetParser().MatchAndEmitInstruction(IDLoc, Info.Opcode, 4499 if (Info.Opcode == ~0U) 4502 const MCInstrDesc &Desc = MII->get(Info.Opcode);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 3104 unsigned Opcode = Def->getOpcode(); local 3105 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 3362 static bool isTargetShuffle(unsigned Opcode) { argument 3363 switch(Opcode) { 5201 unsigned Opcode = V.getOpcode(); local 5217 if (isTargetShuffle(Opcode)) { 5237 if (Opcode == ISD::BITCAST) { 6076 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal 6078 /// For example, if \p Opcode i 6085 isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode, SelectionDAG &DAG, unsigned BaseIdx, unsigned LastIdx, SDValue &V0, SDValue &V1) argument 6262 unsigned Opcode = Op.getOpcode(); local [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/main/ |
H A D | dlist.c | 105 struct gl_list_instruction Opcode[MAX_DLIST_EXT_OPCODES]; member in struct:gl_list_extensions 607 ctx->ListExt->Opcode[i].Destroy(ctx, &node[1]); 608 step = ctx->ListExt->Opcode[i].Size; 619 ctx->ListExt->Opcode[i].Execute(ctx, &node[1]); 620 step = ctx->ListExt->Opcode[i].Size; 631 ctx->ListExt->Opcode[i].Print(ctx, &node[1]); 632 step = ctx->ListExt->Opcode[i].Size; 1057 ctx->ListExt->Opcode[i].Size = 1059 ctx->ListExt->Opcode[i].Execute = execute; 1060 ctx->ListExt->Opcode[ [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 645 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { 646 switch (Opcode) { 988 unsigned Opcode = AArch64ISD::SUBS; local 1003 Opcode = AArch64ISD::ADDS; 1011 Opcode = AArch64ISD::ANDS; 1016 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS) 3234 unsigned Opcode = AArch64ISD::CSEL; local 3278 Opcode = AArch64ISD::CSINV; 3280 Opcode = AArch64ISD::CSNEG; 3291 Opcode 4599 unsigned Opcode; local 4752 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType()); local 5009 unsigned Opcode = N->getOpcode(); local 5498 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType()); local 6445 unsigned Opcode = local 7042 unsigned Opcode; local [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 360 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 5665 const unsigned Opcode = Inst.getOpcode(); local 5666 switch (Opcode) { 5689 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) { 6179 const unsigned Opcode = local 6183 TmpInst.setOpcode(Opcode); 6197 const unsigned Opcode = local 6201 TmpInst.setOpcode(Opcode); 8032 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument 9133 const int64_t Opcode = OC->getValue(); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 761 switch (Opcode) { 7105 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 || local 7112 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ? 7117 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
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/external/mesa3d/src/mesa/main/ |
H A D | dlist.c | 105 struct gl_list_instruction Opcode[MAX_DLIST_EXT_OPCODES]; member in struct:gl_list_extensions 607 ctx->ListExt->Opcode[i].Destroy(ctx, &node[1]); 608 step = ctx->ListExt->Opcode[i].Size; 619 ctx->ListExt->Opcode[i].Execute(ctx, &node[1]); 620 step = ctx->ListExt->Opcode[i].Size; 631 ctx->ListExt->Opcode[i].Print(ctx, &node[1]); 632 step = ctx->ListExt->Opcode[i].Size; 1057 ctx->ListExt->Opcode[i].Size = 1059 ctx->ListExt->Opcode[i].Execute = execute; 1060 ctx->ListExt->Opcode[ [all...] |
/external/owasp/sanitizer/tools/findbugs/lib/ |
H A D | asm-xml-3.3.jar | META-INF/MANIFEST.MF org/objectweb/asm/xml/ASMContentHandler$AnnotationDefaultRule.class " package org.objectweb ... |
H A D | findbugs.jar | META-INF/ META-INF/MANIFEST.MF default.xsl edu/ edu/umd/ edu/umd/cs/ edu/ ... |
/external/clang/lib/Sema/ |
H A D | SemaExpr.cpp | 5972 static bool IsArithmeticBinaryExpr(Expr *E, BinaryOperatorKind *Opcode, argument 5982 *Opcode = OP->getOpcode(); 6002 *Opcode = OpKind; 7752 BinaryOperator::Opcode Opc){
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/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/ |
H A D | org.objectweb.asm_3.2.0.v200909071300.jar | META-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ... |
/external/robolectric/lib/main/ |
H A D | javassist-3.14.0-GA.jar | META-INF/ META-INF/MANIFEST.MF javassist/ javassist/bytecode/ javassist/bytecode/analysis/ javassist/bytecode/annotation/ javassist/ ... |