/external/mesa3d/src/gallium/drivers/r600/ |
H A D | r600.h | 117 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG]; member in struct:r600_pipe_state 234 state->regs[state->nregs].value = value;
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vs_emit.c | 171 * Do things as simply as possible. Allocate and populate all regs 241 /* We can only load 32 regs of push constants. */ 299 c->regs[PROGRAM_STATE_VAR][i] = stride(brw_vec4_grf(reg + i / 2, 310 /* Allocate input regs: 316 c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0); 326 /* Allocate outputs. The non-position outputs go straight into message regs. 334 assert(vert_result < Elements(c->regs[PROGRAM_OUTPUT])); 336 c->regs[PROGRAM_OUTPUT][vert_result] = brw_message_reg(slot + 1); 338 c->regs[PROGRAM_OUTPUT][vert_result] = brw_vec8_grf(reg, 0); 346 c->regs[PROGRAM_TEMPORAR [all...] |
/external/chromium_org/v8/src/ |
H A D | sampler.h | 70 void SampleStack(const RegisterState& regs);
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H A D | sampler.cc | 400 state.fp = reinterpret_cast<Address>(mcontext.regs[29]); 580 const RegisterState& regs) { 583 pc = regs.pc; 606 tos = Memory::Address_at(regs.sp); 610 SafeStackFrameIterator it(isolate, regs.fp, regs.sp, js_entry_sp); 579 Init(Isolate* isolate, const RegisterState& regs) argument
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/external/elfutils/0.153/libdw/ |
H A D | dwarf_frame_register.c | 81 const struct dwarf_frame_register *reg = &fs->regs[regno];
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H A D | cfi.h | 207 struct dwarf_frame_register regs[]; member in struct:Dwarf_Frame_s
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/external/ltrace/sysdeps/linux-gnu/aarch64/ |
H A D | fetch.c | 32 int aarch64_read_gregs(struct process *proc, struct user_pt_regs *regs); 33 int aarch64_read_fregs(struct process *proc, struct user_fpsimd_state *regs); 74 uint64_t u = context->gregs.regs[context->ngrn++]; 314 context->x8 = (arch_addr_t) (uintptr_t) context->gregs.regs[8];
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/external/valgrind/main/coregrind/m_gdbserver/ |
H A D | valgrind-low-mips32.c | 40 static struct reg regs[] = { variable in typeref:struct:reg 116 #define num_regs (sizeof (regs) / sizeof (regs[0])) 359 regs, 360 29, //sp = r29, which is register offset 29 in regs 371 set_register_cache (regs, num_regs);
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H A D | valgrind-low-mips64.c | 40 static struct reg regs[] = { variable in typeref:struct:reg 117 #define num_regs (sizeof (regs) / sizeof (regs[0])) 360 regs, 361 29, //sp = r29, which is register offset 29 in regs 372 set_register_cache (regs, num_regs);
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/external/qemu/target-i386/ |
H A D | cpu.h | 738 target_ulong regs[CPU_NB_REGS]; member in struct:CPUX86State 1038 #define EAX (env->regs[R_EAX]) 1040 #define ECX (env->regs[R_ECX]) 1042 #define EDX (env->regs[R_EDX]) 1044 #define EBX (env->regs[R_EBX]) 1046 #define ESP (env->regs[R_ESP]) 1048 #define EBP (env->regs[R_EBP]) 1050 #define ESI (env->regs[R_ESI]) 1052 #define EDI (env->regs[R_EDI]) 1094 env->regs[R_ES [all...] |
/external/valgrind/main/none/tests/s390x/ |
H A D | cu12.c | 80 cu12_t regs; local 98 regs.addr1 = (uint64_t)dest; 99 regs.len1 = dest_len; 100 regs.addr2 = (uint64_t)source; 101 regs.len2 = source_len; 102 regs.cc = cc; 104 return regs;
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H A D | cu12_1.c | 80 cu12_t regs; local 98 regs.addr1 = (uint64_t)dest; 99 regs.len1 = dest_len; 100 regs.addr2 = (uint64_t)source; 101 regs.len2 = source_len; 102 regs.cc = cc; 104 return regs;
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H A D | cu14.c | 80 cu14_t regs; local 98 regs.addr1 = (uint64_t)dest; 99 regs.len1 = dest_len; 100 regs.addr2 = (uint64_t)source; 101 regs.len2 = source_len; 102 regs.cc = cc; 104 return regs;
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H A D | cu14_1.c | 80 cu14_t regs; local 98 regs.addr1 = (uint64_t)dest; 99 regs.len1 = dest_len; 100 regs.addr2 = (uint64_t)source; 101 regs.len2 = source_len; 102 regs.cc = cc; 104 return regs;
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
H A D | r200_sanity.c | 614 static struct reg regs[Elements(reg_names)+1]; variable in typeref:struct:reg 625 for (i = 0 ; i < Elements(regs) ; i++) { 626 regs[i].idx = reg_names[i].idx; 627 regs[i].closest = ®_names[i]; 628 regs[i].flags = 0; 645 regs[Elements(regs)-1].idx = -1; 792 for (i = 0 ; i < Elements(regs) ; i++) 793 print_reg( ®s[i] ); 828 struct reg *reg = lookup_reg( regs, packe [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
H A D | radeon_sanity.c | 336 static struct reg regs[Elements(reg_names)+1]; variable in typeref:struct:reg 347 for (i = 0 ; i < Elements(regs)-1 ; i++) { 348 regs[i].idx = reg_names[i].idx; 349 regs[i].closest = ®_names[i]; 350 regs[i].flags = 0; 367 regs[Elements(regs)-1].idx = -1; 514 for (i = 0 ; i < Elements(regs) ; i++) 515 print_reg( ®s[i] ); 550 struct reg *reg = lookup_reg( regs, packe [all...] |
/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | r200_sanity.c | 614 static struct reg regs[Elements(reg_names)+1]; variable in typeref:struct:reg 625 for (i = 0 ; i < Elements(regs) ; i++) { 626 regs[i].idx = reg_names[i].idx; 627 regs[i].closest = ®_names[i]; 628 regs[i].flags = 0; 645 regs[Elements(regs)-1].idx = -1; 792 for (i = 0 ; i < Elements(regs) ; i++) 793 print_reg( ®s[i] ); 828 struct reg *reg = lookup_reg( regs, packe [all...] |
/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_sanity.c | 336 static struct reg regs[Elements(reg_names)+1]; variable in typeref:struct:reg 347 for (i = 0 ; i < Elements(regs)-1 ; i++) { 348 regs[i].idx = reg_names[i].idx; 349 regs[i].closest = ®_names[i]; 350 regs[i].flags = 0; 367 regs[Elements(regs)-1].idx = -1; 514 for (i = 0 ; i < Elements(regs) ; i++) 515 print_reg( ®s[i] ); 550 struct reg *reg = lookup_reg( regs, packe [all...] |
/external/vixl/src/a64/ |
H A D | macro-assembler-a64.h | 272 void PushXRegList(RegList regs) { argument 273 PushSizeRegList(regs, kXRegSize); 275 void PopXRegList(RegList regs) { argument 276 PopSizeRegList(regs, kXRegSize); 278 void PushWRegList(RegList regs) { argument 279 PushSizeRegList(regs, kWRegSize); 281 void PopWRegList(RegList regs) { argument 282 PopSizeRegList(regs, kWRegSize); 284 inline void PushDRegList(RegList regs) { argument 285 PushSizeRegList(regs, kDRegSiz 287 PopDRegList(RegList regs) argument 290 PushSRegList(RegList regs) argument 293 PopSRegList(RegList regs) argument [all...] |
/external/chromium_org/v8/src/arm64/ |
H A D | macro-assembler-arm64.h | 593 inline void PushXRegList(RegList regs) { argument 594 PushSizeRegList(regs, kXRegSizeInBits); 596 inline void PopXRegList(RegList regs) { argument 597 PopSizeRegList(regs, kXRegSizeInBits); 599 inline void PushWRegList(RegList regs) { argument 600 PushSizeRegList(regs, kWRegSizeInBits); 602 inline void PopWRegList(RegList regs) { argument 603 PopSizeRegList(regs, kWRegSizeInBits); 605 inline void PushDRegList(RegList regs) { argument 606 PushSizeRegList(regs, kDRegSizeInBit 608 PopDRegList(RegList regs) argument 611 PushSRegList(RegList regs) argument 614 PopSRegList(RegList regs) argument [all...] |
/external/kernel-headers/original/uapi/asm-arm64/asm/ |
H A D | kvm.h | 44 struct user_pt_regs regs; /* sp = sp_el0 */ member in struct:kvm_regs
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/external/lldb/source/Plugins/Process/POSIX/ |
H A D | RegisterContext_i386.cpp | 150 (offsetof(RegisterContext_i386::UserArea, regs) + \ 530 log->Printf("%12s = 0x%8.8" PRIx64, g_register_infos[reg].name, ((uint64_t*)&user.regs)[reg]); 541 result = monitor.ReadGPR(m_thread.GetID(), &user.regs, sizeof(user.regs));
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H A D | RegisterContext_i386.h | 142 GPR regs; // General purpose registers. member in struct:RegisterContext_i386::UserArea
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/external/strace/ |
H A D | syscall.c | 884 /* tprintf("[%016lx] ", aarch64_regs.regs[???]); */ 1347 scno = aarch64_regs.regs[8]; 1399 unsigned long long regs[38]; 1401 if (ptrace(PTRACE_GETREGS, tcp->pid, NULL, (long) ®s) < 0) 1403 mips_a3 = regs[REG_A3]; 1404 mips_r2 = regs[REG_V0]; 1534 scno = tile_regs.regs[10]; 1789 unsigned long long regs[38]; 1791 if (ptrace(PTRACE_GETREGS, tcp->pid, NULL, (long) ®s) < 0) 1795 tcp->u_arg[i] = regs[REG_A [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_ppc.c | 87 * We have 32 PPC vector regs. Use 16 of them for storing 4 TGSI temps. 100 } regs[12]; /* 3 src regs, 4 channels */ member in struct:gen_context 424 if (equal_src_locs(&gen->regs[i].src, gen->regs[i].chan, src, chan)) { 426 assert(gen->regs[i].vec >= 0); 427 return gen->regs[i].vec; 433 gen->regs[gen->num_regs].src = *src; 434 gen->regs[gen->num_regs].chan = chan; 435 gen->regs[ge [all...] |