| /external/llvm/unittests/Support/ |
| H A D | YAMLIOTest.cpp | 883 a2, enumerator in enum:AFlags
915 io.enumCase(value, "a2", a2);
960 Input yin("---\n - kind: A\n flags: a2\n - kind: B\n flags: b1\n...\n");
966 EXPECT_EQ(seq[0].flags, (uint32_t)a2);
980 seq.push_back(KindAndFlags(kindA,a2));
1000 EXPECT_EQ(seq2[2].flags, (uint32_t)a2);
|
| /external/lzma/C/ |
| H A D | CpuArch.c | 57 UInt32 a2, b2, c2, d2;
local
63 __asm mov a2, EAX;
local
68 *a = a2;
|
| /external/lzma/CPP/7zip/Archive/7z/ |
| H A D | 7zDecode.cpp | 45 const NCoderMixer::CCoderStreamsInfo &a2)
47 return (a1.NumInStreams == a2.NumInStreams) &&
48 (a1.NumOutStreams == a2.NumOutStreams);
51 static bool AreBindPairsEqual(const NCoderMixer::CBindPair &a1, const NCoderMixer::CBindPair &a2)
argument
53 return (a1.InIndex == a2.InIndex) &&
54 (a1.OutIndex == a2.OutIndex);
57 static bool AreBindInfoExEqual(const CBindInfoEx &a1, const CBindInfoEx &a2)
argument
59 if (a1.Coders.Size() != a2.Coders.Size())
63 if (!AreCodersEqual(a1.Coders[i], a2.Coders[i]))
65 if (a1.BindPairs.Size() != a2
44 AreCodersEqual(const NCoderMixer::CCoderStreamsInfo &a1, const NCoderMixer::CCoderStreamsInfo &a2) argument
[all...] |
| H A D | 7zUpdate.cpp | 83 static int CompareBuffers(const CByteBuffer &a1, const CByteBuffer &a2)
argument
86 size_t c2 = a2.GetCapacity();
89 RINOZ_COMP(a1[i], a2[i]);
293 const CRefItem &a2 = *p2;
local
295 const CUpdateItem &u2 = *a2.UpdateItem;
309 RINOZ_COMP(a1.ExtensionIndex, a2.ExtensionIndex);
310 RINOZ(MyStringCompareNoCase(u1.Name + a1.ExtensionPos, u2.Name + a2.ExtensionPos));
311 RINOZ(MyStringCompareNoCase(u1.Name + a1.NamePos, u2.Name + a2.NamePos));
|
| /external/lzma/CPP/Common/ |
| H A D | MyVector.h | 261 static int CompareObjectItems(void *const *a1, void *const *a2, void * /* param */)
argument
262 { return MyCompare(*(*((const T **)a1)), *(*((const T **)a2))); }
|
| /external/llvm/test/MC/Mips/ |
| H A D | mips-fpu-instructions.s | 179 cfc1 $a2,$0
181 mfc1 $a2,$f7
186 mtc1 $a2,$f7
203 luxc1 $f0, $a2($a1)
|
| H A D | mips-register-names-o32.s | 14 addiu $a2, $zero, 0 # CHECK: encoding: [0x24,0x06,0x00,0x00]
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 26 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 27 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 26 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
88 sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 13 addu $9,$a0,$a2
29 ctc1 $a2,$26
49 lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
60 move $25,$a2
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 22 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips32.s | 21 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips32r2.s | 27 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 25 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 24 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
71 sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 13 addu $9,$a0,$a2
31 ctc1 $a2,$26
57 lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
68 move $25,$a2
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 13 addu $9,$a0,$a2
34 ctc1 $a2,$26
62 dmultu $a1,$a2
108 lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
121 move $25,$a2
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips64.s | 8 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 13 addu $9,$a0,$a2
36 ctc1 $a2,$26
63 lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
70 mfc0 $a2,$14,1
78 move $25,$a2
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 13 addu $9,$a0,$a2
36 ctc1 $a2,$26
72 lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
82 mfc0 $a2,$14,1
91 move $25,$a2
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64.s | 11 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips64r2.s | 10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 13 addu $9,$a0,$a2
36 ctc1 $a2,$26
64 dmultu $a1,$a2
111 lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
125 move $25,$a2
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64.s | 10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|