Searched defs:Op (Results 201 - 225 of 272) sorted by relevance

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/external/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp127 auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc); local
128 Op->Token.Data = Str.data();
129 Op->Token.Length = Str.size();
130 return Op;
134 auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc); local
135 Op->Reg.Kind = Kind;
136 Op->Reg.Num = Num;
137 return Op;
141 auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc); local
142 Op
147 auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc); local
155 auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc); local
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp206 LowerOperation(SDValue Op, SelectionDAG &DAG) const { argument
207 switch (Op.getOpcode())
209 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
210 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
211 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
212 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
213 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
214 case ISD::LOAD: return LowerLOAD(Op, DAG);
215 case ISD::STORE: return LowerSTORE(Op, DAG);
216 case ISD::VAARG: return LowerVAARG(Op, DA
286 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument
317 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument
328 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument
350 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const argument
423 LowerLOAD(SDValue Op, SelectionDAG &DAG) const argument
502 LowerSTORE(SDValue Op, SelectionDAG &DAG) const argument
561 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const argument
578 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const argument
600 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, SDValue &Addend1, bool requireIntermediatesHaveOneUse) argument
754 LowerVAARG(SDValue Op, SelectionDAG &DAG) const argument
780 LowerVASTART(SDValue Op, SelectionDAG &DAG) const argument
792 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument
809 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const argument
828 LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const argument
837 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const argument
876 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const argument
881 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const argument
937 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument
954 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const argument
960 LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const argument
991 LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const argument
1841 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp121 // the Op parameter is 'OP', OpRHS is 'C1', and AndRHS is 'C2'. Op is
123 Instruction *InstCombiner::OptAndOp(Instruction *Op, argument
127 Value *X = Op->getOperand(0);
129 if (!Op->isShift())
132 switch (Op->getOpcode()) {
134 if (Op->hasOneUse()) {
137 And->takeName(Op);
142 if (Op->hasOneUse()){
146 Or->takeName(Op);
1889 FoldOrWithConstants(BinaryOperator &I, Value *Op, Value *A, Value *B, Value *C) argument
[all...]
/external/llvm/utils/TableGen/
H A DAsmMatcherEmitter.cpp656 MatchableInfo::AsmOperand &Op);
690 AsmOperand &Op = AsmOperands[i]; local
691 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
692 errs() << '\"' << Op.Token << "\"\n";
739 ResOperand &Op = ResOperands[i]; local
740 if (Op.Kind == ResOperand::RenderAsmOperand &&
741 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
742 Op.AsmOperandNum = DstAsmOperand;
751 ResOperand &Op = ResOperands[i]; local
752 switch(Op
1300 MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; local
1422 MatchableInfo::AsmOperand &Op = II->AsmOperands[i]; local
1507 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx]; local
1564 buildAliasOperandReference(MatchableInfo *II, StringRef OperandName, MatchableInfo::AsmOperand &Op) argument
[all...]
/external/skia/src/animator/
H A DSkScript2.h57 enum Op { // used by tokenizer attribute table enum in class:SkScriptEngine2
191 Branch(Op op, int depth, size_t offset)
208 Op fOperator : 6; // operand which generated branch
248 void processLogicalOp(Op op);
257 SkTDStack<Op> fOpStack;
/external/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyTIL.h114 StringRef getUnaryOpcodeString(TIL_UnaryOpcode Op);
115 StringRef getBinaryOpcodeString(TIL_BinaryOpcode Op);
280 SExpr(TIL_Opcode Op) : Opcode(Op), Reserved(0), Flags(0) {} argument
337 unsigned Op = E->opcode(); local
338 return Op == COP_Variable || Op == COP_Literal || Op == COP_LiteralPtr;
501 TIL_Opcode Op = Ptr->opcode();
502 if (Op
1236 UnaryOp(TIL_UnaryOpcode Op, SExpr *E) argument
1272 BinaryOp(TIL_BinaryOpcode Op, SExpr *E0, SExpr *E1) argument
1320 Cast(TIL_CastOpcode Op, SExpr *E) argument
[all...]
/external/clang/lib/AST/
H A DExprConstant.cpp1608 unsigned BitWidth, Operation Op) {
1610 return Op(LHS, RHS);
1612 APSInt Value(Op(LHS.extend(BitWidth), RHS.extend(BitWidth)), false);
1606 CheckedIntArithmetic(EvalInfo &Info, const Expr *E, const APSInt &LHS, const APSInt &RHS, unsigned BitWidth, Operation Op) argument
/external/clang/lib/Sema/
H A DSemaOpenMP.cpp1462 auto Op = CE->getOperator(); local
1463 switch (Op) {
1469 return SetUB(CE->getArg(1), Op == OO_Less || Op == OO_LessEqual,
1470 Op == OO_Less || Op == OO_Greater, CE->getSourceRange(),
1473 return SetUB(CE->getArg(0), Op == OO_Greater || Op == OO_GreaterEqual,
1474 Op == OO_Less || Op
1958 PerformOpenMPImplicitIntegerConversion(SourceLocation Loc, Expr *Op) argument
[all...]
/external/clang/utils/TableGen/
H A DNeonEmitter.cpp1419 std::string Op = DefI->getAsString(); local
1421 if (Op == "cast" || Op == "bitcast")
1422 return emitDagCast(DI, Op == "bitcast");
1423 if (Op == "shuffle")
1425 if (Op == "dup")
1427 if (Op == "splat")
1429 if (Op == "save_temp")
1431 if (Op == "op")
1433 if (Op
1444 std::string Op = cast<StringInit>(DI->getArg(0))->getAsUnquotedString(); local
[all...]
/external/llvm/include/llvm/IR/
H A DIRBuilder.h952 AtomicRMWInst *CreateAtomicRMW(AtomicRMWInst::BinOp Op, Value *Ptr, Value *Val, argument
955 return Insert(new AtomicRMWInst(Op, Ptr, Val, Ordering, SynchScope));
1190 Value *CreateCast(Instruction::CastOps Op, Value *V, Type *DestTy, argument
1195 return Insert(Folder.CreateCast(Op, VC, DestTy), Name);
1196 return Insert(CastInst::Create(Op, V, DestTy), Name);
/external/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinter.cpp616 const MachineOperand &Op = MI->getOperand(i); local
617 assert(Op.isReg() && "KILL instruction must have only register operands");
619 Str += AP.TM.getRegisterInfo()->getName(Op.getReg());
620 Str += (Op.isDef() ? "<def>" : "<kill>");
1622 Constant *Op = CE->getOperand(0); local
1623 Op = ConstantExpr::getIntegerCast(Op, DL.getIntPtrType(CV->getType()),
1625 return lowerConstant(Op, AP);
1632 Constant *Op = CE->getOperand(0); local
1635 const MCExpr *OpExpr = lowerConstant(Op, A
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp153 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); local
154 return GetPromotedInteger(Op);
159 SDValue Op = SExtPromotedInteger(N->getOperand(0)); local
161 Op.getValueType(), Op, N->getOperand(1));
166 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); local
168 Op.getValueType(), Op, N->getOperand(1));
293 SDValue Op = GetPromotedInteger(N->getOperand(0)); local
295 EVT NVT = Op
340 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); local
354 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); local
359 SDValue Op = GetPromotedInteger(N->getOperand(0)); local
580 SDValue Op = GetPromotedInteger(N->getOperand(0)); local
888 SDValue Op = GetPromotedInteger(N->getOperand(0)); local
1052 SDValue Op = GetPromotedInteger(N->getOperand(0)); local
1077 SDValue Op = GetPromotedInteger(N->getOperand(0)); local
1088 SDValue Op = GetPromotedInteger(N->getOperand(0)); local
1692 SDValue Op = N->getOperand(0); local
1826 SDValue Op = N->getOperand(0); local
1838 SDValue Op = N->getOperand(0); local
2171 SDValue Op = N->getOperand(0); local
2409 SDValue Op = N->getOperand(0); local
2692 SDValue Op = N->getOperand(0); local
2795 SDValue Op = N->getOperand(0); local
2905 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext); local
2945 SDValue Op; local
2972 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0)); local
2996 SDValue Op = N->getOperand(i); local
[all...]
H A DTargetLowering.cpp282 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, argument
284 SDLoc dl(Op);
287 switch (Op.getOpcode()) {
292 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
295 if (Op.getOpcode() == ISD::XOR &&
301 EVT VT = Op.getValueType();
302 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
306 return CombineTo(Op, New);
321 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, argument
372 SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth) const argument
1087 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
1104 ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &, unsigned Depth) const argument
2101 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument
2531 ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG) argument
2582 ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG) const argument
2772 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const argument
[all...]
/external/llvm/lib/IR/
H A DConstants.cpp273 if (ConstantExpr *Op = dyn_cast<ConstantExpr>(CE->getOperand(i))) {
274 if (NonTrappingOps.insert(Op) && canTrapImpl(Op, NonTrappingOps))
317 for (const Value *Op : WorkItem->operands()) {
318 const Constant *ConstOp = dyn_cast<Constant>(Op);
1128 ConstantExpr::getWithOperandReplaced(unsigned OpNo, Constant *Op) const {
1129 assert(Op->getType() == getOperand(OpNo)->getType() &&
1131 if (getOperand(OpNo) == Op)
1136 NewOps.push_back(i == OpNo ? Op : getOperand(i));
1408 &Op<
2812 Constant *Op = getOperand(i); local
[all...]
H A DInstructions.cpp126 Op<-1>().set(nullptr);
268 Op<-1>() = Func;
290 Op<-1>() = Func;
534 Op<-3>() = Fn;
535 Op<-2>() = IfNormal;
536 Op<-1>() = IfException;
621 Op<0>() = RI.Op<0>();
630 Op<0>() = retVal;
637 Op<
1846 Create(BinaryOps Op, Value *S1, Value *S2, const Twine &Name, Instruction *InsertBefore) argument
1854 Create(BinaryOps Op, Value *S1, Value *S2, const Twine &Name, BasicBlock *InsertAtEnd) argument
1862 CreateNeg(Value *Op, const Twine &Name, Instruction *InsertBefore) argument
1870 CreateNeg(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument
1878 CreateNSWNeg(Value *Op, const Twine &Name, Instruction *InsertBefore) argument
1884 CreateNSWNeg(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument
1890 CreateNUWNeg(Value *Op, const Twine &Name, Instruction *InsertBefore) argument
1896 CreateNUWNeg(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument
1902 CreateFNeg(Value *Op, const Twine &Name, Instruction *InsertBefore) argument
1909 CreateFNeg(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument
1916 CreateNot(Value *Op, const Twine &Name, Instruction *InsertBefore) argument
1923 CreateNot(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument
3085 Create(OtherOps Op, unsigned short predicate, Value *S1, Value *S2, const Twine &Name, Instruction *InsertBefore) argument
3106 Create(OtherOps Op, unsigned short predicate, Value *S1, Value *S2, const Twine &Name, BasicBlock *InsertAtEnd) argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp801 const Value *Op = *i; local
804 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
809 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
814 if (canFoldAddIntoGEP(U, Op)) {
817 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
820 Op = cast<AddOperator>(Op)->getOperand(0);
1518 unsigned Op = getRegForValue(V); local
1519 if (Op == 0) return false;
1524 .addReg(Op));
1537 unsigned Op = getRegForValue(V); local
1601 unsigned Op = getRegForValue(I->getOperand(0)); local
2211 Value *Op = I->getOperand(i); local
2570 Value *Op = I->getOperand(0); local
[all...]
H A DARMISelDAGToDAG.cpp142 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
144 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
146 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
151 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
156 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
183 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
260 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
803 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, argument
805 unsigned Opcode = Op->getOpcode();
807 ? cast<LoadSDNode>(Op)
839 SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
859 SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
934 SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
1021 SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset) argument
1340 SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, SDValue &OffImm) argument
3452 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) argument
[all...]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1165 unsigned Op = Shift | (imm << 3); local
1166 Inst.addOperand(MCOperand::CreateImm(Op));
1522 ARM_AM::AddrOpc Op = ARM_AM::add;
1524 Op = ARM_AM::sub;
1559 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1564 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp356 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, argument
358 switch(Op.getOpcode()) {
359 case ISD::LOAD: return lowerLOAD(Op, DAG);
360 case ISD::STORE: return lowerSTORE(Op, DAG);
361 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
362 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
363 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
364 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
365 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
366 case ISD::SDIVREM: return lowerMulDiv(Op, MipsIS
1194 lowerLOAD(SDValue Op, SelectionDAG &DAG) const argument
1226 lowerSTORE(SDValue Op, SelectionDAG &DAG) const argument
1256 lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, SelectionDAG &DAG) const argument
1289 extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) argument
1307 lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1356 lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1369 lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) argument
1398 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) argument
1438 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument
1481 lowerMSABitClear(SDValue Op, SelectionDAG &DAG) argument
1491 lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) argument
1501 lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument
2147 lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) argument
2161 lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const argument
2215 lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) argument
2229 lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const argument
2269 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const argument
2288 isConstantOrUndef(const SDValue Op) argument
2298 isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) argument
2318 lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const argument
2413 lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2471 lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2501 lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2531 lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2561 lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2592 lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2618 lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2642 lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2693 lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const argument
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp485 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { argument
486 SDLoc dl(Op);
487 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
488 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
489 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
1017 // Op to just print "call"
1258 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1259 SDNode *Node = Op.getNode();
1281 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op, argument
1283 assert(Op
1342 LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const argument
1398 LowerOperation(SDValue Op, SelectionDAG &DAG) const argument
1427 LowerLOAD(SDValue Op, SelectionDAG &DAG) const argument
1438 LowerLOADi1(SDValue Op, SelectionDAG &DAG) const argument
1457 LowerSTORE(SDValue Op, SelectionDAG &DAG) const argument
1468 LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const argument
1556 LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const argument
2107 LowerAsmOperandForConstraint( SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument
2862 IsMulWideOperandDemotable(SDValue Op, unsigned OptSize, OperandSignedness &S) argument
[all...]
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp521 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, argument
523 switch (Op.getOpcode()) {
525 Op.getNode()->dump();
529 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
530 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
531 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
532 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
533 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
534 case ISD::SDIV: return LowerSDIV(Op, DAG);
535 case ISD::SREM: return LowerSREM(Op, DA
671 LowerGlobalAddress(AMDGPUMachineFunction* MFI, SDValue Op, SelectionDAG &DAG) const argument
742 LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const argument
754 LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const argument
766 LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const argument
781 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument
921 LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const argument
933 LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const argument
1003 SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const argument
1039 MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const argument
1097 SplitVectorStore(SDValue Op, SelectionDAG &DAG) const argument
1123 LowerLOAD(SDValue Op, SelectionDAG &DAG) const argument
1222 LowerSTORE(SDValue Op, SelectionDAG &DAG) const argument
1279 LowerSDIV24(SDValue Op, SelectionDAG &DAG) const argument
1360 LowerSDIV32(SDValue Op, SelectionDAG &DAG) const argument
1425 LowerSDIV64(SDValue Op, SelectionDAG &DAG) const argument
1429 LowerSDIV(SDValue Op, SelectionDAG &DAG) const argument
1447 LowerSREM32(SDValue Op, SelectionDAG &DAG) const argument
1508 LowerSREM64(SDValue Op, SelectionDAG &DAG) const argument
1512 LowerSREM(SDValue Op, SelectionDAG &DAG) const argument
1524 LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const argument
1628 LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const argument
1666 LowerFCEIL(SDValue Op, SelectionDAG &DAG) const argument
1689 LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const argument
1745 LowerFRINT(SDValue Op, SelectionDAG &DAG) const argument
1769 LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const argument
1776 LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const argument
1799 LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const argument
1818 ExpandSIGN_EXTEND_INREG(SDValue Op, unsigned BitsDiff, SelectionDAG &DAG) const argument
1830 LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const argument
1858 isU24(SDValue Op, SelectionDAG &DAG) argument
1866 isI24(SDValue Op, SelectionDAG &DAG) argument
1876 simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) argument
2180 computeKnownBitsForTargetNode( const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
2246 ComputeNumSignBitsForTargetNode( SDValue Op, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1708 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1709 /// be zero. Op is expected to be a target specific node. Used by DAG
1712 (const SDValue Op,
1720 switch (Op.getOpcode()) {
1725 DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1726 DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1759 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, argument
1761 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1767 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1773 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1711 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
1788 makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const argument
1800 makeAddress(SDValue Op, SelectionDAG &DAG) const argument
1848 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument
1853 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument
1858 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument
1863 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const argument
1999 LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const argument
2153 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2169 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2186 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2215 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2243 LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2264 LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2283 LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2320 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2356 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2376 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument
2399 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2423 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument
2430 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2469 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2478 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument
2514 LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) argument
2543 LowerF128Load(SDValue Op, SelectionDAG &DAG) argument
2594 LowerF128Store(SDValue Op, SelectionDAG &DAG) argument
2637 LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) argument
2669 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument
2720 LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2765 LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) argument
2776 LowerOperation(SDValue Op, SelectionDAG &DAG) const argument
3102 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument
[all...]
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp92 ICToken Op = PostfixStack.pop_back_val(); local
93 assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
95 return Op.second;
97 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) { argument
98 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
100 PostfixStack.push_back(std::make_pair(Op, Val));
104 void pushOperator(InfixCalculatorTok Op) { argument
107 InfixOperatorStack.push_back(Op);
166 ICToken Op = PostfixStack[i]; local
1647 HandleAVX512Operand(OperandVector &Operands, const MCParsedAsmOperand &Op) argument
2006 X86Operand &Op = (X86Operand &)*Operands.back(); local
2018 X86Operand &Op = (X86Operand &)*Operands[1]; local
2091 X86Operand &Op = (X86Operand &)*Operands[1]; local
2117 X86Operand &Op = (X86Operand &)*Operands[1]; local
2292 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]); local
[all...]
/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp733 const Value *Op = *i; local
736 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue());
744 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
749 if (canFoldAddIntoGEP(U, Op)) {
752 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
755 Op = cast<AddOperator>(Op)->getOperand(0);
763 IndexReg = getRegForGEPIndex(Op).first;
1045 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : local
1047 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
2515 const Value *Op = I.getArgOperand(0); local
[all...]
H A DX86ISelDAGToDAG.cpp231 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
1718 enum AtomicOpc &Op, MVT NVT,
1726 if (Op == ADD) {
1729 Op = (CNVal == 1) ? INC : DEC;
1735 Op = SUB;
1743 if (Op == ADD && Val.hasOneUse()) {
1746 Op = SUB;
1755 Op = SUB;
1782 enum AtomicOpc Op; local
1787 Op
1716 getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG, SDLoc dl, enum AtomicOpc &Op, MVT NVT, SDValue Val) argument
1975 SDValue Op = Chain.getOperand(i); local
2167 unsigned ShlOp, Op; local
2761 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) argument
[all...]

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