Searched defs:Reg (Results 201 - 225 of 253) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp162 unsigned Reg = lookUpRegForValue(V); local
163 if (Reg != 0)
164 return Reg;
177 Reg = materializeRegForValue(V, VT);
181 return Reg;
188 unsigned Reg = 0; local
192 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
194 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
198 Reg =
202 Reg
271 UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) argument
587 unsigned Reg = getRegForValue(Val); local
876 unsigned Reg = getRegForValue(I->getOperand(0)); local
1192 unsigned Reg = getRegForValue(I->getOperand(0)); local
1663 unsigned Reg = getRegForValue(PHIOp); local
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H A DScheduleDAGRRList.cpp1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
237 void releaseInterferences(unsigned Reg = 0);
291 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); local
292 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
1137 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, argument
1173 SDep FromDep(SU, SDep::Data, Reg);
1192 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, argument
1198 if (Reg == *ImpDef)
1207 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, argument
1212 for (MCRegAliasIterator AliasI(Reg, TR
1291 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); local
1330 releaseInterferences(unsigned Reg) argument
1397 unsigned Reg = LRegs[j]; local
1440 unsigned Reg = LRegs[0]; local
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H A DSelectionDAGBuilder.h238 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
240 /// Reg - the virtual register containing the index of the jump table entry
242 unsigned Reg; member in struct:llvm::SelectionDAGBuilder::JumpTable
280 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
285 unsigned Reg; member in struct:llvm::SelectionDAGBuilder::BitTestBlock
588 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
683 unsigned Reg,
H A DSelectionDAGISel.cpp470 unsigned Reg = local
472 if (TargetRegisterInfo::isPhysicalRegister(Reg))
475 MachineInstr *Def = RegInfo->getVRegDef(Reg);
482 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
485 // If Reg is live-in then update debug info to track its copy in a vreg.
486 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
911 if (unsigned Reg = TLI->getExceptionPointerRegister())
912 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
915 if (unsigned Reg = TLI->getExceptionSelectorRegister())
916 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrR
1864 unsigned Reg = getTargetLowering()->getRegisterByName( local
1877 unsigned Reg = getTargetLowering()->getRegisterByName( local
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/external/llvm/lib/MC/
H A DMCDwarf.cpp1108 unsigned Reg = Instr.getRegister(); local
1111 Streamer.AddComment(Twine("Reg ") + Twine(Reg));
1114 Streamer.EmitULEB128IntValue(Reg);
1143 Streamer.AddComment(Twine("Reg ") + Twine(Instr.getRegister()));
1161 Streamer.AddComment(Twine("Reg ") + Twine(Instr.getRegister()));
1172 unsigned Reg = Instr.getRegister(); local
1181 if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Reg));
1182 Streamer.EmitULEB128IntValue(Reg);
1210 unsigned Reg = Instr.getRegister(); local
1218 unsigned Reg = Instr.getRegister(); local
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/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp54 unsigned Reg; member in union:__anon25940::AArch64FastISel::Address::__anon25942
60 Address() : Kind(RegBase), Offset(0) { Base.Reg = 0; }
65 void setReg(unsigned Reg) { argument
67 Base.Reg = Reg;
71 return Base.Reg;
1594 unsigned Reg = getRegForValue(RV); local
1595 if (Reg == 0)
1598 unsigned SrcReg = Reg + VA.getValNo();
H A DAArch64ISelDAGToDAG.cpp75 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
78 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) { argument
79 return SelectShiftedRegister(N, false, Reg, Shift);
81 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) { argument
82 return SelectShiftedRegister(N, true, Reg, Shift);
165 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
319 SDValue &Reg, SDValue &Shift) {
331 Reg = N.getOperand(0);
535 bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg, argument
552 Reg
318 SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg, SDValue &Shift) argument
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/external/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp1814 unsigned Reg = CmpMI->getOperand(0).getReg(); local
1818 isARMLowRegister(Reg)) {
1823 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
H A DARMFrameLowering.cpp219 unsigned Reg = CSI[i].getReg(); local
221 switch (Reg) {
241 if (Reg == FramePtr)
247 if (Reg == ARM::D8)
249 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
379 unsigned Reg = Entry.getReg(); local
381 switch (Reg) {
400 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
444 unsigned Reg local
480 unsigned Reg = Entry.getReg(); local
816 unsigned Reg = CSI[i-1].getReg(); local
894 unsigned Reg = CSI[i-1].getReg(); local
1432 unsigned Reg = CSRegs[i]; local
1556 unsigned Reg = UnspilledCS1GPRs[i]; local
1567 unsigned Reg = UnspilledCS2GPRs.front(); local
1585 unsigned Reg = UnspilledCS1GPRs.back(); local
1597 unsigned Reg = UnspilledCS2GPRs.back(); local
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H A DARMLoadStoreOptimizer.cpp85 unsigned Reg; member in struct:__anon25980::ARMLoadStoreOpt::MemOpQueueEntry
92 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
632 unsigned Reg = memOps[i].Reg; local
633 KilledRegs.insert(Reg);
634 Killer[Reg] = i;
642 unsigned Reg = memOps[i].Reg; local
645 bool isKill = memOps[i].isKill || KilledRegs.count(Reg);
646 Regs.push_back(std::make_pair(Reg, isKil
686 unsigned Reg = Regs[i-memOpsBegin].first; local
746 unsigned Reg = MO.getReg(); local
1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1531 unsigned Reg = MO.getReg(); local
1842 unsigned Reg = MO.getReg(); local
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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h210 static inline bool isARMLowRegister(unsigned Reg) { argument
212 switch (Reg) {
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp120 /// If successful, it will return true and set the \p Reg, \p IVBump
130 bool findInductionRegister(MachineLoop *L, unsigned &Reg,
236 unsigned Reg; member in struct:__anon26012::CountValue::Values::__anon26013
246 Contents.R.Reg = v;
257 return Contents.R.Reg;
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
320 unsigned &Reg,
416 Reg = F->second.first;
900 unsigned Reg = MO.getReg(); local
901 if (MRI->use_nodbg_empty(Reg))
319 findInductionRegister(MachineLoop *L, unsigned &Reg, int64_t &IVBump, MachineInstr *&IVOp ) const argument
954 unsigned Reg = MO.getReg(); local
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H A DHexagonISelLowering.cpp191 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
206 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
216 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
217 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
262 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
263 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
277 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
278 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocV
720 unsigned Reg = local
987 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); local
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp663 unsigned NVPTXAsmPrinter::encodeVirtualRegister(unsigned Reg) { argument
664 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
665 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
668 unsigned RegNum = RegMap[Reg];
695 return Reg & 0x0FFFFFFF;
894 NVPTXAsmPrinter::getVirtualRegisterName(unsigned Reg) const {
895 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
904 VRegMap::const_iterator VI = RegMap.find(Reg);
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp71 unsigned Reg; member in union:__anon26084::Address::__anon26086
80 Base.Reg = 0;
382 if (Addr.Base.Reg == 0)
383 Addr.Base.Reg = getRegForValue(Obj);
387 if (Addr.Base.Reg != 0)
388 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
390 return Addr.Base.Reg != 0;
410 Addr.Base.Reg = ResultReg;
507 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
531 .addReg(Addr.Base.Reg)
1554 unsigned Reg = getRegForValue(RV); local
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H A DPPCISelDAGToDAG.cpp172 /// register can be improved, but it is wrong to substitute Reg+Reg for
173 /// Reg in an asm, because the load or store opcode would have to change.
212 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
213 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
1442 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; local
1445 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
H A DPPCInstrInfo.cpp116 unsigned Reg = DefMO.getReg(); local
120 if (TRI->isVirtualRegister(Reg)) {
123 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
124 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
126 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
127 PPC::CRBITRCRegClass.contains(Reg);
993 unsigned Reg, MachineRegisterInfo *MRI) const {
1017 UseMI->getOperand(UseIdx).getReg() == Reg)
1020 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1021 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
992 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument
1889 IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, MachineRegisterInfo &MRI) argument
1900 IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) argument
1904 IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) argument
1908 IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) argument
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/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp598 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local
599 MFI->LiveOuts.push_back(Reg);
600 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
631 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local
634 MRI.addLiveIn(Reg);
636 SDLoc(DAG.getEntryNode()), Reg, VT);
1683 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); local
1684 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2106 if (RegisterSDNode *Reg =
2108 if (Reg
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H A DSIISelLowering.cpp413 unsigned Reg = VA.getLocReg(); local
417 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
419 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
420 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
426 Reg = MF.addLiveIn(Reg, RC);
427 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, V
510 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); local
524 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); local
539 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); local
1273 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg(); local
1713 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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H A DSIInstrInfo.cpp395 unsigned Reg = MI->getOperand(1).getReg(); local
398 MI->getOperand(2).ChangeToRegister(Reg, false);
586 unsigned Reg = MI->getOperand(i).getReg(); local
587 if (TargetRegisterInfo::isVirtualRegister(Reg))
591 if (!RC->contains(Reg)) {
772 unsigned Reg = MRI.createVirtualRegister(VRC); local
774 Reg).addOperand(MO);
775 MO.ChangeToRegister(Reg, false);
1205 unsigned Reg = Inst->getOperand(0).getReg(); local
1209 MRI.getRegClass(Reg),
1527 unsigned Reg = NewDesc.ImplicitUses[i]; local
1534 unsigned Reg = NewDesc.ImplicitDefs[i]; local
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/external/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp101 RegOp Reg; member in union:__anon26144::SystemZOperand::__anon26145
135 Op->Reg.Kind = Kind;
136 Op->Reg.Num = Num;
178 return Kind == KindReg && Reg.Kind == RegKind;
182 return Reg.Num;
311 bool parseRegister(Register &Reg);
313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
419 bool SystemZAsmParser::parseRegister(Register &Reg) { argument
420 Reg.StartLoc = Parser.getTok().getLoc();
429 return Error(Reg
460 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) argument
512 Register Reg; local
528 Register Reg; local
585 Register Reg; local
652 Register Reg; local
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/external/llvm/utils/TableGen/
H A DAsmMatcherEmitter.cpp382 static ResOperand getRegOp(Record *Reg) { argument
385 X.Register = Reg;
787 if (Record *Reg = AsmOperands[i].SingletonReg)
788 SingletonRegisters.insert(Reg);
952 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
953 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
961 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
962 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
1143 CI->ClassName = "Reg" + utostr(Index);
1682 Record *Reg local
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H A DCodeGenRegisters.cpp142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]); local
143 ExplicitAliases.push_back(Reg);
144 Reg->ExplicitAliases.push_back(this);
586 Record *Reg = Lists[i][n]; variable
588 Name += Reg->getName();
589 Tuple.push_back(DefInit::get(Reg));
591 unsigned(Reg->getValueAsInt("CostPerUse")));
691 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]); local
692 Members.insert(Reg);
693 TopoSigs.set(Reg
703 CodeGenRegister *Reg = RegBank.getReg(Order.back()); local
1032 CodeGenRegister *&Reg = Def2Reg[Def]; local
1294 const CodeGenRegister *Reg = Registers[i]; local
1315 const CodeGenRegister *Reg = nullptr; local
1366 normalizeWeight(CodeGenRegister *Reg, std::vector<UberRegSet> &UberSets, std::vector<UberRegSet*> &RegSets, std::set<unsigned> &NormalRegs, CodeGenRegister::RegUnitList &NormalUnits, CodeGenRegBank &RegBank) argument
1924 const CodeGenRegister *Reg = getReg(R); local
1969 CodeGenRegister *Reg = getReg(Regs[i]); local
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H A DDAGISelMatcher.h878 /// Reg - The def for the register that we're emitting. If this is null, then
880 const CodeGenRegister *Reg; member in class:llvm::EmitRegisterMatcher
884 : Matcher(EmitRegister), Reg(reg), VT(vt) {}
886 const CodeGenRegister *getReg() const { return Reg; }
896 return cast<EmitRegisterMatcher>(M)->Reg == Reg &&
900 return ((unsigned)(intptr_t)Reg) << 4 | VT;
/external/qemu/target-i386/
H A Dops_sse.h21 #define Reg MMXReg macro
29 #define Reg XMMReg macro
38 void glue(helper_psrlw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
62 void glue(helper_psraw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
83 void glue(helper_psllw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
107 void glue(helper_psrld, SUFFIX)(CPUX86State *env, Reg *d, Reg *
2297 #undef Reg macro
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