Searched refs:MI (Results 201 - 225 of 514) sorted by relevance

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/external/llvm/lib/Target/R600/
H A DAMDGPUMCInstLower.cpp55 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument
57 OutMI.setOpcode(getMCOpcode(MI->getOpcode()));
59 for (const MachineOperand &MO : MI->explicit_operands()) {
85 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument
91 if (!TM.getInstrInfo()->verifyInstruction(MI, Err)) {
93 MI->dump();
96 if (MI->isBundle()) {
97 const MachineBasicBlock *MBB = MI->getParent();
98 MachineBasicBlock::const_instr_iterator I = MI;
106 MCInstLowering.lower(MI, TmpIns
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/external/llvm/lib/Analysis/IPA/
H A DFindUsedTypes.cpp69 for (Module::iterator MI = m.begin(), ME = m.end(); MI != ME; ++MI) {
70 IncorporateType(MI->getType());
71 const Function &F = *MI;
/external/llvm/lib/CodeGen/
H A DLivePhysRegs.cpp36 void LivePhysRegs::stepBackward(const MachineInstr &MI) { argument
38 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
51 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
65 void LivePhysRegs::stepForward(const MachineInstr &MI) { argument
68 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
H A DCriticalAntiDepBreaker.cpp95 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, argument
104 if (MI->isDebugValue() || MI->isKill())
128 PrescanInstruction(MI);
129 ScanInstruction(MI, Count);
154 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { argument
171 bool Special = MI->isCall() ||
172 MI->hasExtraSrcRegAllocReq() ||
173 TII->isPredicated(MI);
177 for (unsigned i = 0, e = MI
242 ScanInstruction(MachineInstr *MI, unsigned Count) argument
537 MachineInstr *MI = --I; local
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H A DRegisterScavenging.cpp116 MachineInstr *MI = MBBI; local
117 assert(!MI->isDebugValue() && "Debug values have no kills or defs");
124 bool isPred = TII->isPredicated(MI);
127 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
128 const MachineOperand &MO = MI->getOperand(i);
156 MachineInstr *MI = MBBI; local
157 if (!MI->isDebugValue()) {
183 MachineInstr *MI = MBBI; local
187 if (I->Restore != MI)
194 if (MI
297 MachineBasicBlock::iterator MI = StartMI; local
352 getFrameIndexOperandNum(MachineInstr *MI) argument
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H A DMachineVerifier.cpp200 void visitMachineBundleBefore(const MachineInstr *MI);
201 void visitMachineInstrBefore(const MachineInstr *MI);
203 void visitMachineInstrAfter(const MachineInstr *MI);
204 void visitMachineBundleAfter(const MachineInstr *MI);
210 void report(const char *msg, const MachineInstr *MI);
221 void verifyInlineAsm(const MachineInstr *MI);
402 void MachineVerifier::report(const char *msg, const MachineInstr *MI) { argument
403 assert(MI);
404 report(msg, MI->getParent());
406 if (Indexes && Indexes->hasIndex(MI))
707 visitMachineBundleBefore(const MachineInstr *MI) argument
731 verifyInlineAsm(const MachineInstr *MI) argument
773 visitMachineInstrBefore(const MachineInstr *MI) argument
817 const MachineInstr *MI = MO->getParent(); local
987 const MachineInstr *MI = MO->getParent(); local
1114 visitMachineInstrAfter(const MachineInstr *MI) argument
1121 visitMachineBundleAfter(const MachineInstr *MI) argument
1390 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def); local
1483 const MachineInstr *MI = local
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H A DStackMaps.cpp38 PatchPointOpers::PatchPointOpers(const MachineInstr *MI) argument
39 : MI(MI),
40 HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
41 !MI->getOperand(0).isImplicit()),
42 IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg)
45 unsigned CheckStartIdx = 0, e = MI->getNumOperands();
46 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
47 MI
192 recordStackMapOpers(const MachineInstr &MI, uint64_t ID, MachineInstr::const_mop_iterator MOI, MachineInstr::const_mop_iterator MOE, bool recordResult) argument
243 recordStackMap(const MachineInstr &MI) argument
251 recordPatchPoint(const MachineInstr &MI) argument
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/external/llvm/lib/Target/ARM/
H A DARMFrameLowering.h35 MachineBasicBlock::iterator MI,
40 MachineBasicBlock::iterator MI,
59 void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
64 void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
73 MachineBasicBlock::iterator MI) const override;
H A DThumb2InstrInfo.cpp437 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
440 unsigned Opcode = MI.getOpcode();
441 const MCInstrDesc &Desc = MI.getDesc();
450 Offset += MI.getOperand(FrameRegIdx+1).getImm();
453 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
455 MI.setDesc(TII.get(ARM::tMOVr));
456 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
458 do MI.RemoveOperand(FrameRegIdx+1);
459 while (MI.getNumOperands() > FrameRegIdx+1);
460 MachineInstrBuilder MIB(*MI
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H A DThumb1RegisterInfo.cpp323 static void removeOperands(MachineInstr &MI, unsigned i) {
325 for (unsigned e = MI.getNumOperands(); i != e; ++i)
326 MI.RemoveOperand(Op);
347 MachineInstr &MI = *II;
348 MachineBasicBlock &MBB = *MI.getParent();
349 DebugLoc dl = MI.getDebugLoc();
350 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
351 unsigned Opcode = MI.getOpcode();
352 const MCInstrDesc &Desc = MI.getDesc();
356 Offset += MI
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/external/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp71 void insertCallDefsUses(MachineBasicBlock::iterator MI,
75 void insertDefsUses(MachineBasicBlock::iterator MI,
116 MachineBasicBlock::iterator MI = I; local
119 // If MI is restore, try combining it with previous inst.
121 (MI->getOpcode() == SP::RESTORErr
122 || MI->getOpcode() == SP::RESTOREri)) {
123 Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
128 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
129 || MI
275 insertCallDefsUses(MachineBasicBlock::iterator MI, SmallSet<unsigned, 32>& RegDefs, SmallSet<unsigned, 32>& RegUses) argument
304 insertDefsUses(MachineBasicBlock::iterator MI, SmallSet<unsigned, 32>& RegDefs, SmallSet<unsigned, 32>& RegUses) argument
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H A DSparcAsmPrinter.cpp53 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
54 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
56 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
59 void EmitInstruction(const MachineInstr *MI) override;
66 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
69 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
73 void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
175 void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, argument
181 const MachineOperand &MO = MI->getOperand(0);
258 void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) argument
297 printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) argument
385 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier) argument
409 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
430 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
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/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.cpp61 MCInst &MI, raw_ostream &CommentStream, int64_t Value, uint64_t Address,
91 } else if (MI.getOpcode() == AArch64::ADRP) {
99 EncodedInst |= MCRI.getEncodingValue(MI.getOperand(0).getReg()); // reg
104 } else if (MI.getOpcode() == AArch64::ADDXri ||
105 MI.getOpcode() == AArch64::LDRXui ||
106 MI.getOpcode() == AArch64::LDRXl ||
107 MI.getOpcode() == AArch64::ADR) {
108 if (MI.getOpcode() == AArch64::ADDXri)
110 else if (MI.getOpcode() == AArch64::LDRXui)
112 if (MI
60 tryAddingSymbolicOperand( MCInst &MI, raw_ostream &CommentStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp273 MachineInstr &MI = *II; local
275 MachineBasicBlock &MBB = *MI.getParent();
284 DebugLoc dl = MI.getDebugLoc();
321 bool KillNegSizeReg = MI.getOperand(1).isKill();
322 unsigned NegSizeReg = MI.getOperand(1).getReg();
348 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
373 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
393 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> local
395 MachineBasicBlock &MBB = *MI.getParent();
398 DebugLoc dl = MI
437 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> local
510 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> local
553 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> local
600 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> local
625 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> local
671 usesIXAddr(const MachineInstr &MI) argument
686 getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum) argument
703 MachineInstr &MI = *II; local
885 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const argument
963 resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const argument
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H A DPPCInstrInfo.h109 bool isCoalescableExtInstr(const MachineInstr &MI,
112 unsigned isLoadFromStackSlot(const MachineInstr *MI,
114 unsigned isStoreToStackSlot(const MachineInstr *MI,
119 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
121 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
125 MachineBasicBlock::iterator MI) const override;
144 MachineBasicBlock::iterator MI, DebugLoc DL,
200 bool isPredicated(const MachineInstr *MI) const override;
202 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
204 bool PredicateInstruction(MachineInstr *MI,
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/external/llvm/lib/Target/Mips/
H A DMips16HardFloat.cpp190 std::string MI = ToFP? "mtc1 ": "mfc1 "; local
193 IAH.Out(MI + "$$4,$$f12");
196 IAH.Out(MI +"$$4,$$f12");
197 IAH.Out(MI + "$$5,$$f14");
200 IAH.Out(MI + "$$4,$$f12");
202 IAH.Out(MI + "$$6,$$f14");
203 IAH.Out(MI + "$$7,$$f15");
205 IAH.Out(MI + "$$7,$$f14");
206 IAH.Out(MI + "$$6,$$f15");
211 IAH.Out(MI
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H A DMipsOptimizePICCall.cpp77 /// \brief Test if MI jumps to a function via a register.
82 bool isCallViaRegister(MachineInstr &MI, unsigned &Reg,
103 /// Return the first MachineOperand of MI if it is a used virtual register.
104 static MachineOperand *getCallTargetRegOpnd(MachineInstr &MI) { argument
105 if (MI.getNumOperands() == 0)
108 MachineOperand &MO = MI.getOperand(0);
141 /// Search MI's operands for register GP and erase it.
142 static void eraseGPOpnd(MachineInstr &MI) { argument
146 MachineFunction &MF = *MI.getParent()->getParent();
147 MVT::SimpleValueType Ty = getRegTy(MI
246 isCallViaRegister(MachineInstr &MI, unsigned &Reg, ValueType &Val) const argument
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H A DMipsConstantIslandPass.cpp80 static unsigned int branchTargetOperand(MachineInstr *MI) { argument
81 switch (MI->getOpcode()) {
266 MachineInstr *MI; member in struct:__anon26048::MipsConstantIslands::CPUser
279 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp),
284 /// getMaxDisp - Returns the maximum displacement supported by MI.
328 MachineInstr *MI; member in struct:__anon26048::MipsConstantIslands::ImmBranch
333 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
384 unsigned getOffsetOf(MachineInstr *MI) const;
394 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
407 bool isCPEntryInRange(MachineInstr *MI, unsigne
879 splitBlockBeforeInstr(MachineInstr *MI) argument
1008 isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, MachineInstr *CPEMI, unsigned MaxDisp, bool NegOk, bool DoDump) argument
1314 MachineBasicBlock::iterator MI = UserMI; local
1499 isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB, unsigned MaxDisp) argument
1527 MachineInstr *MI = Br.MI; local
1546 MachineInstr *MI = Br.MI; local
1587 MachineInstr *MI = Br.MI; local
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/external/llvm/lib/Target/X86/
H A DX86VZeroUpper.cpp125 static bool hasYmmReg(MachineInstr *MI) { argument
126 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
127 const MachineOperand &MO = MI->getOperand(i);
128 if (MI->isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO))
142 static bool callClobbersAnyYmmReg(MachineInstr *MI) { argument
143 assert(MI->isCall() && "Can only be called on call instructions.");
144 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
145 const MachineOperand &MO = MI->getOperand(i);
183 MachineInstr *MI = I; local
184 bool isControlFlow = MI
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/external/llvm/lib/Target/Hexagon/
H A DHexagonMCInstLower.cpp42 void llvm::HexagonLowerToMC(const MachineInstr* MI, HexagonMCInst& MCI, argument
44 MCI.setOpcode(MI->getOpcode());
45 MCI.setDesc(MI->getDesc());
47 for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) {
48 const MachineOperand &MO = MI->getOperand(i);
53 MI->dump();
H A DHexagonCopyToCombine.cpp87 MachineBasicBlock::iterator &MI, bool DoInsertAtI1);
113 static bool isCombinableInstType(MachineInstr *MI, argument
116 switch(MI->getOpcode()) {
119 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg());
121 unsigned DestReg = MI->getOperand(0).getReg();
122 unsigned SrcReg = MI->getOperand(1).getReg();
130 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
131 unsigned DestReg = MI
210 removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) argument
361 MachineInstr *MI = I; local
512 combine(MachineInstr *I1, MachineInstr *I2, MachineBasicBlock::iterator &MI, bool DoInsertAtI1) argument
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/external/llvm/include/llvm/CodeGen/
H A DRegisterPressure.h177 /// Store the effects of a change in pressure on things that MI scheduler cares
307 /// Get the MI position corresponding to this register pressure.
310 // Reset the MI position corresponding to the register pressure. This allows
364 void getMaxUpwardPressureDelta(const MachineInstr *MI,
370 void getUpwardPressureDelta(const MachineInstr *MI,
380 void getMaxDownwardPressureDelta(const MachineInstr *MI,
388 void getMaxPressureDelta(const MachineInstr *MI,
393 return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,
397 return getMaxUpwardPressureDelta(MI, nullptr, Delta, CriticalPSets,
402 void getUpwardPressure(const MachineInstr *MI,
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUConvertToISA.cpp57 MachineInstr &MI = *I; local
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
H A DR600ISelLowering.h27 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
41 void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
/external/llvm/lib/CodeGen/AsmPrinter/
H A DDbgValueHistoryCalculator.h37 void startInstrRange(const MDNode *Var, const MachineInstr &MI);
38 void endInstrRange(const MDNode *Var, const MachineInstr &MI);

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