/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 39 const AArch64TargetMachine *TM; member in class:__anon25950::final 48 AArch64TTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) { 52 AArch64TTI(const AArch64TargetMachine *TM) argument 53 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()), 54 TLI(TM->getTargetLowering()) { 137 llvm::createAArch64TargetTransformInfoPass(const AArch64TargetMachine *TM) { argument 138 return new AArch64TTI(TM);
|
H A D | AArch64A53Fix835769.cpp | 110 const TargetMachine &TM = F.getTarget(); local 115 TII = TM.getSubtarget<AArch64Subtarget>().getInstrInfo();
|
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDILISelDAGToDAG.cpp | 41 AMDGPUDAGToDAGISel(TargetMachine &TM); 82 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM 84 return new AMDGPUDAGToDAGISel(TM); 87 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM 89 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>())
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 99 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel) argument 100 : SelectionDAGISel(TM, OptLevel), 101 Lowering(*TM.getTargetLowering()), 102 Subtarget(*TM.getSubtargetImpl()) { } 131 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM, argument 133 return new MSP430DAGToDAGISel(TM, OptLevel);
|
/external/llvm/tools/opt/ |
H A D | opt.cpp | 461 std::unique_ptr<TargetMachine> TM(Machine); 464 if (TM.get()) 465 TM->addAnalysisPasses(Passes); 472 if (TM.get()) 473 TM->addAnalysisPasses(*FPasses); 544 P = PassInf->getTargetMachineCtor()(TM.get());
|
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelDAGToDAG.cpp | 41 AMDGPUDAGToDAGISel(TargetMachine &TM); 82 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM 84 return new AMDGPUDAGToDAGISel(TM); 87 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM 89 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>())
|
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetMachine.cpp | 98 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM) argument 99 : TargetPassConfig(TM, PM) {}
|
H A D | NVPTX.h | 63 createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel);
|
H A D | NVPTXSubtarget.h | 58 const std::string &FS, const TargetMachine &TM, bool is64Bit);
|
H A D | NVPTXPrologEpilogPass.cpp | 50 const TargetMachine &TM = MF.getTarget(); local 51 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 52 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCSubtarget.h | 124 const std::string &FS, PPCTargetMachine &TM, bool is64Bit, 187 const TargetMachine &TM) const;
|
H A D | PPCTargetMachine.cpp | 78 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) argument 79 : TargetPassConfig(TM, PM) {}
|
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZShortenInst.cpp | 51 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) { argument 52 return new SystemZShortenInst(TM);
|
/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | LLVMConventionsChecker.cpp | 88 TemplateName TM = TS->getTemplateName(); 89 TemplateDecl *TD = TM.getAsTemplateDecl(); 102 TemplateName TM = TS->getTemplateName(); 103 TemplateDecl *TD = TM.getAsTemplateDecl();
|
/external/llvm/include/llvm/CodeGen/ |
H A D | DFAPacketizer.h | 94 const TargetMachine &TM; member in class:llvm::VLIWPacketizerList
|
/external/llvm/include/llvm/Transforms/ |
H A D | Scalar.h | 126 Pass *createGlobalMergePass(const TargetMachine *TM = nullptr);
|
/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinterDwarf.cpp | 133 return TM.getDataLayout()->getPointerSize(); 149 TLOF.getTTypeGlobalReference(GV, Encoding, *Mang, TM, MMI, OutStreamer); 252 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 334 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
|
H A D | ErlangGCPrinter.cpp | 53 unsigned IntPtrSize = AP.TM.getDataLayout()->getPointerSize();
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.h | 27 explicit MipsSEInstrInfo(MipsTargetMachine &TM);
|
H A D | MipsSubtarget.h | 145 MipsTargetMachine *TM; member in class:llvm::MipsSubtarget 179 MipsTargetMachine *TM); 279 const TargetMachine *TM);
|
/external/llvm/lib/Target/R600/ |
H A D | AMDGPU.h | 58 createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM);
|
/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 29 : CallingConv(CC), IsVarArg(isVarArg), MF(mf), TM(tm), 30 TRI(*TM.getRegisterInfo()), Locs(locs), Context(C), 53 TM.getTargetLowering()->HandleByVal(this, Size, Align);
|
H A D | MachineFunction.cpp | 54 MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM, argument 57 : Fn(F), Target(TM), Ctx(mmi.getContext()), MMI(mmi), GMI(gmi) { 58 if (TM.getRegisterInfo()) 59 RegInfo = new (Allocator) MachineRegisterInfo(TM); 65 new (Allocator) MachineFrameInfo(TM,!F->hasFnAttribute("no-realign-stack")); 72 ConstantPool = new (Allocator) MachineConstantPool(TM); 73 Alignment = TM.getTargetLowering()->getMinFunctionAlignment(); 79 TM.getTargetLowering()->getPrefFunctionAlignment()); 487 return TM.getFrameLowering(); 602 const TargetMachine &TM local [all...] |
/external/llvm/lib/ExecutionEngine/MCJIT/ |
H A D | MCJIT.h | 211 TargetMachine *TM; member in class:llvm::MCJIT 318 TargetMachine *getTargetMachine() override { return TM; } 332 TargetMachine *TM);
|
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 30 : CallingConv(CC), IsVarArg(isVarArg), TM(tm), Locs(locs), Context(c) { 34 UsedRegs.resize((TM.getRegisterInfo()->getNumRegs()+31)/32); 58 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
|