/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 115 unsigned getRegBinaryCode(unsigned reg) const; 119 unsigned getHWRegNum(unsigned reg) const; 232 // Add one to skip over the destination reg operand. 236 unsigned reg = MI.getOperand(opIdx).getReg(); local 237 if (AMDGPUMCRegisterClasses[AMDGPU::VReg_32RegClassID].contains(reg) || 238 AMDGPUMCRegisterClasses[AMDGPU::VReg_64RegClassID].contains(reg)) { 293 unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const { 294 switch (reg) { 297 default: return getHWRegNum(reg);
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/external/mesa3d/src/gallium/drivers/svga/svgadump/ |
H A D | svga_shader_dump.c | 131 const struct sh_reg reg, 134 if (reg.relative) { 138 _debug_printf("%s[aL+%u]", name, reg.number); 140 _debug_printf("%s[a%u.x+%u]", name, indreg->number, reg.number); 143 _debug_printf("%s%u", name, reg.number); 147 static void dump_reg( struct sh_reg reg, struct sh_srcreg *indreg, const struct dump_info *di ) argument 149 assert( reg.is_reg == 1 ); 151 switch (sh_reg_type( reg )) { 153 format_reg("r", reg, NULL); 157 format_reg("v", reg, indre 130 format_reg(const char *name, const struct sh_reg reg, const struct sh_srcreg *indreg) argument 361 struct sh_reg reg; member in union:__anon27544 [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_clip.h | 103 } reg; member in struct:brw_clip_compile
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H A D | brw_fs_emit.cpp | 393 * Otherwise, we can use an implied move from g0 to the first message reg. 518 * reg where we have active channels. 538 /* Unlike the 965, we have the mask reg, so we just need 541 * written. Use the flag reg for consistency with gen6+. 653 static uint32_t brw_file_from_reg(fs_reg *reg) argument 655 switch (reg->file) { 671 brw_reg_from_fs_reg(fs_reg *reg) argument 675 switch (reg->file) { 679 if (reg->smear == -1) { 680 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), re [all...] |
H A D | brw_fs_schedule_instructions.cpp | 280 add_dep(last_grf_write[inst->src[i].reg], n); 308 add_dep(last_grf_write[inst->dst.reg], n); 309 last_grf_write[inst->dst.reg] = n; 311 int reg = inst->dst.reg & ~BRW_MRF_COMPR4; local 313 add_dep(last_mrf_write[reg], n); 314 last_mrf_write[reg] = n; 316 if (inst->dst.reg & BRW_MRF_COMPR4) 317 reg += 4; 319 reg 395 int reg = inst->dst.reg & ~BRW_MRF_COMPR4; local [all...] |
H A D | brw_sf_emit.c | 51 static inline int vert_reg_to_vert_result(struct brw_sf_compile *c, GLuint reg, argument 54 int vue_slot = (reg + c->urb_entry_read_offset) * 2 + half; 244 GLuint reg, i; local 266 reg = 3; 268 c->vert[i] = brw_vec8_grf(reg, 0); 269 reg += c->nr_attr_regs; 272 /* Temporaries, allocated after last vertex reg. 274 c->inv_det = brw_vec1_grf(reg, 0); reg++; 275 c->a1_sub_a0 = brw_vec8_grf(reg, 326 calculate_masks(struct brw_sf_compile *c, GLuint reg, GLushort *pc, GLushort *pc_persp, GLushort *pc_linear) argument 378 calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg) argument [all...] |
/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | r200_blit.c | 33 int reg, int count) 36 return CP_PACKET0(reg, count - 1); 32 cmdpacket0(struct radeon_screen *rscrn, int reg, int count) argument
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_blit.c | 33 int reg, int count) 36 return CP_PACKET0(reg, count - 1); 32 cmdpacket0(struct radeon_screen *rscrn, int reg, int count) argument
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/external/pcre/dist/sljit/ |
H A D | sljitNativeX86_64.c | 29 static sljit_si emit_load_imm64(struct sljit_compiler *compiler, sljit_si reg, sljit_sw imm) argument 36 *inst++ = REX_W | ((reg_map[reg] <= 7) ? 0 : REX_B); 37 *inst++ = MOV_r_i32 + (reg_map[reg] & 0x7);
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/external/qemu/target-i386/ |
H A D | misc_helper.c | 130 target_ulong helper_read_crN(CPUX86State *env, int reg) argument 135 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) argument 139 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0) argument 143 target_ulong helper_read_crN(CPUX86State *env, int reg) argument 147 helper_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0); 148 switch(reg) { 150 val = env->cr[reg]; 163 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) argument 165 helper_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0); 166 switch(reg) { 188 helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0) argument [all...] |
/external/tcpdump/ |
H A D | print-mpcp.c | 141 const struct mpcp_reg_t *reg; member in union:__anon31535 244 mpcp.reg = (const struct mpcp_reg_t *)tptr; 247 EXTRACT_16BITS(mpcp.reg->assigned_port), 248 bittok2str(mpcp_reg_flag_values, "Reserved", mpcp.reg->flags), 249 EXTRACT_16BITS(mpcp.reg->sync_time), 250 mpcp.reg->echoed_pending_grants);
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/external/valgrind/main/VEX/priv/ |
H A D | host_generic_regs.h | 50 - Whether or not the register is a virtual reg. 73 UInt reg; member in struct:__anon31910 124 r.reg = regno | (((UInt)rc) << 28) | (virtual ? (1<<24) : 0); 129 UInt rc = r.reg; 136 return r.reg & 0x00FFFFFF; 140 return toBool(r.reg & (1<<24)); 145 return toBool(r1.reg == r2.reg); 156 /*--- Recording register usage (for reg-alloc) ---*/ 186 create duplicate entries -- each reg shoul [all...] |
/external/valgrind/main/VEX/useful/ |
H A D | show_fp_state.c | 21 UChar reg[80]; member in struct:__anon32343 102 printf ( "%02x", (UInt)m_fpu_state.reg[j]);
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H A D | x87_to_vex_and_back.c | 29 UChar reg[80]; member in struct:__anon32345 65 convert_f80le_to_f64le( &x87->reg[FP_REG(r)], (UChar*)&vexRegs[r] ); 101 convert_f64le_to_f80le( (UChar*)&vexRegs[r], &x87->reg[FP_REG(r)] ); 105 convert_f64le_to_f80le( (UChar*)&vexRegs[r], &x87->reg[FP_REG(r)] ); 233 printf ( "%02x", (UInt)x87->reg[j]);
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/external/valgrind/main/memcheck/tests/amd64/ |
H A D | bt_everything.c | 410 ULong reg; local 457 reg = 0; 464 case 0: c = btsl_reg(reg, bitoff, ®); break; 465 case 1: c = btrl_reg(reg, bitoff, ®); break; 466 case 2: c = btcl_reg(reg, bitoff, ®); break; 467 case 3: c = btl_reg(reg, bitoff, ®); brea [all...] |
/external/vixl/test/ |
H A D | test-utils-a64.cc | 97 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg) { argument 98 VIXL_ASSERT(reg.Is32Bits()); 101 int64_t result_x = core->xreg(reg.code()); 107 uint32_t result_w = core->wreg(reg.code()); 114 const Register& reg) { 115 VIXL_ASSERT(reg.Is64Bits()); 116 uint64_t result = core->xreg(reg.code()); 112 Equal64(uint64_t expected, const RegisterDump* core, const Register& reg) argument
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/external/wpa_supplicant_8/hostapd/src/p2p/ |
H A D | p2p_utils.c | 335 const struct p2p_reg_class *reg = &channels->reg_class[i]; local 336 if (reg->reg_class != reg_class) 338 for (j = 0; j < reg->channels; j++) { 339 if (reg->channel[j] == channel) 352 const struct p2p_reg_class *reg = &channels->reg_class[i]; local 353 for (j = 0; j < reg->channels; j++) { 354 if (p2p_channel_to_freq(reg->reg_class, 355 reg->channel[j]) == (int) freq)
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/external/wpa_supplicant_8/src/p2p/ |
H A D | p2p_utils.c | 335 const struct p2p_reg_class *reg = &channels->reg_class[i]; local 336 if (reg->reg_class != reg_class) 338 for (j = 0; j < reg->channels; j++) { 339 if (reg->channel[j] == channel) 352 const struct p2p_reg_class *reg = &channels->reg_class[i]; local 353 for (j = 0; j < reg->channels; j++) { 354 if (p2p_channel_to_freq(reg->reg_class, 355 reg->channel[j]) == (int) freq)
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/external/wpa_supplicant_8/wpa_supplicant/src/p2p/ |
H A D | p2p_utils.c | 335 const struct p2p_reg_class *reg = &channels->reg_class[i]; local 336 if (reg->reg_class != reg_class) 338 for (j = 0; j < reg->channels; j++) { 339 if (reg->channel[j] == channel) 352 const struct p2p_reg_class *reg = &channels->reg_class[i]; local 353 for (j = 0; j < reg->channels; j++) { 354 if (p2p_channel_to_freq(reg->reg_class, 355 reg->channel[j]) == (int) freq)
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/external/chromium_org/third_party/mach_override/libudis86/ |
H A D | decode.c | 364 int reg; local 367 case REGCLASS_GPR : reg = decode_gpr(u, size, num); break; 368 case REGCLASS_MMX : reg = UD_R_MM0 + (num & 7); break; 369 case REGCLASS_XMM : reg = UD_R_XMM0 + num; break; 370 case REGCLASS_CR : reg = UD_R_CR0 + num; break; 371 case REGCLASS_DB : reg = UD_R_DR0 + num; break; 380 reg = UD_R_ES + (num & 7); 389 opr->base = reg; 449 * Decodes reg field of mod/rm byte 458 uint8_t reg local [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_tgsi_aos.c | 104 const struct tgsi_full_src_register * reg, 114 assert(!reg->Register.Indirect); 128 reg->Register.Index * 4 + chan); 134 lp_build_name(scalar, "const[%u].%c", reg->Register.Index, "xyzw"[chan]); 175 const struct tgsi_full_src_register * reg, 180 LLVMValueRef res = bld->immediates[reg->Register.Index]; 188 const struct tgsi_full_src_register * reg, 193 LLVMValueRef res = bld->inputs[reg->Register.Index]; 194 assert(!reg->Register.Indirect); 202 const struct tgsi_full_src_register * reg, 102 emit_fetch_constant( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) argument 173 emit_fetch_immediate( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) argument 186 emit_fetch_input( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) argument 200 emit_fetch_temporary( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) argument 228 const struct tgsi_full_dst_register *reg = &inst->Dst[index]; local [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
H A D | i915_fpc_translate.c | 114 negate(int reg, int x, int y, int z, int w) argument 117 return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) | 190 i915_program_error(p, "Exceeded max temporary reg"); 671 tmp, /* dest reg: a dummy reg */ 686 tmp, /* dest reg: a dummy reg */ 1350 depth, /* dest reg */
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir_from_tgsi.cpp | 50 : reg(src->Register), 54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { } 58 struct tgsi_src_register reg; local 59 memset(®, 0, sizeof(reg)); 60 reg.Index = off.Index; 61 reg.File = off.File; 62 reg.SwizzleX = off.SwizzleX; 63 reg.SwizzleY = off.SwizzleY; 64 reg 111 const struct tgsi_src_register reg; member in class:tgsi::Instruction::SrcRegister 152 const struct tgsi_dst_register reg; member in class:tgsi::Instruction::DstRegister [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/ |
H A D | r600_hw_context.c | 132 const struct r600_reg *reg, int index, int nreg, 141 block->start_offset = reg[i].offset; 144 block->reg = &block->pm4[block->pm4_ndwords]; 152 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) { 155 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) { 162 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) { 166 if (reg[i+j].flags & REG_FLAG_NEED_BO) { 175 (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) { 177 block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags; 184 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigne argument 130 r600_init_block(struct r600_context *ctx, struct r600_block *block, const struct r600_reg *reg, int index, int nreg, unsigned opcode, unsigned offset_base) argument 713 r600_reg_set_block_reloc(struct r600_pipe_reg *reg) argument 760 struct r600_pipe_reg *reg = &state->regs[i]; local 770 struct r600_pipe_reg *reg = &state->regs[i]; local 783 struct r600_pipe_reg *reg = &state->regs[i]; local [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/svga/svgadump/ |
H A D | svga_shader.h | 60 sh_reg_type( struct sh_reg reg ) 62 return reg.type_lo | (reg.type_hi << 3); 73 struct sh_reg reg; member in struct:sh_def 80 struct sh_reg reg; member in struct:sh_defb 92 struct sh_reg reg; member in struct:sh_defi 142 sh_dstreg_type( struct sh_dstreg reg ) 144 return reg.type_lo | (reg.type_hi << 3); 154 struct sh_dstreg reg; member in struct:sh_dcl [all...] |