/external/llvm/lib/CodeGen/ |
H A D | LocalStackSlotAllocation.cpp | 391 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); local 392 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
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H A D | MachineRegisterInfo.cpp | 46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument 47 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 48 VRegInfo[Reg].first = RC; 53 const TargetRegisterClass *RC, 56 if (OldRC == RC) 57 return RC; 59 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 52 constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
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H A D | RegisterScavenging.cpp | 259 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { 260 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 272 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { argument 274 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 362 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, argument 367 TRI->getAllocatableSet(*I->getParent()->getParent(), RC); 381 BitVector Available = getRegsAvailable(RC); 413 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SRe [all...] |
H A D | StackMaps.cpp | 124 const TargetRegisterClass *RC = local 128 Location(Location::Register, RC->getSize(), MOI->getReg(), 0));
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H A D | TargetRegisterInfo.cpp | 87 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 88 if (!RC || RC->isAllocatable()) 89 return RC; 91 const unsigned *SubClass = RC->getSubClassMask(); 118 const TargetRegisterClass* RC = *I; local 119 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 120 (!BestRC || BestRC->hasSubClass(RC))) 121 BestRC = RC; 130 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument 235 const TargetRegisterClass *RC = local [all...] |
H A D | VirtRegMap.cpp | 76 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { argument 77 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 78 RC->getAlignment()); 105 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); local 106 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
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H A D | MachineCSE.cpp | 141 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC, 151 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 152 if (!MRI->constrainRegClass(SrcReg, RC))
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H A D | MachineSSAUpdater.cpp | 116 const TargetRegisterClass *RC, 119 unsigned NewVR = MRI->createVirtualRegister(RC); 114 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
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H A D | PHIElimination.cpp | 260 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); local 261 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 133 const TargetRegisterClass *RC = nullptr; local 135 RC = TRI->getAllocatableClass( 139 UseRC = RC; 140 else if (RC) { 142 TRI->getCommonSubClass(UseRC, RC); 220 const TargetRegisterClass *RC = local 229 if (RC) 230 VTRC = TRI->getCommonSubClass(RC, VTRC); 232 RC = VTRC; 251 if (RegRC == RC) { 288 const TargetRegisterClass *RC = local [all...] |
H A D | ResourcePriorityQueue.cpp | 371 const TargetRegisterClass *RC = *I; local 372 RegBalance += rawRegPressureDelta(SU, RC->getID()); 378 const TargetRegisterClass *RC = *I; local 379 if ((RegPressure[RC->getID()] + 380 rawRegPressureDelta(SU, RC->getID()) > 0) && 381 (RegPressure[RC->getID()] + 382 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) 383 RegBalance += rawRegPressureDelta(SU, RC->getID()); 491 const TargetRegisterClass *RC local 502 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); local [all...] |
H A D | ScheduleDAGSDNodes.cpp | 128 const TargetRegisterClass *RC = local 130 Cost = RC->getCopyCost();
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.cpp | 139 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 140 if (RC == &AArch64::CCRRegClass) 142 return RC; 365 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument 369 switch (RC->getID()) {
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local 267 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC, 320 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local 321 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 77 const TargetRegisterClass *RC = local 80 V0 = RegInfo.createVirtualRegister(RC); 81 V1 = RegInfo.createVirtualRegister(RC); 82 V2 = RegInfo.createVirtualRegister(RC);
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H A D | MipsOptimizePICCall.cpp | 119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); local 120 assert(RC->vt_end() - RC->vt_begin() == 1); 121 return *RC->vt_begin();
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 353 const TargetRegisterClass *RC, 367 if (RC == &SP::I64RegsRegClass) 370 else if (RC == &SP::IntRegsRegClass) 373 else if (RC == &SP::FPRegsRegClass) 376 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 379 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 391 const TargetRegisterClass *RC, 404 if (RC == &SP::I64RegsRegClass) 407 else if (RC == &SP::IntRegsRegClass) 410 else if (RC 351 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 389 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 96 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, argument 104 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); 121 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{ 130 if (RC == &X86::GR8_NOREXRegClass) 131 return RC; 133 const TargetRegisterClass *Super = RC; 134 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 150 if (Super->getSize() == RC->getSize()) 155 return RC; 186 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) cons 197 getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const argument [all...] |
H A D | X86VZeroUpper.cpp | 261 const TargetRegisterClass *RC = &X86::VR256RegClass; local 262 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end();
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 372 const TargetRegisterClass *RC, 395 const TargetRegisterClass *RC, 368 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 392 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 314 const TargetRegisterClass *RC, 320 VirtualRegister = MRI.createVirtualRegister(RC); 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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H A D | AMDGPUInstrInfo.cpp | 126 const TargetRegisterClass *RC, 135 const TargetRegisterClass *RC, 233 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/chromium_org/third_party/harfbuzz-ng/src/ |
H A D | hb-ot-shape-complex-thai.cc | 40 RC, enumerator in enum:thai_consonant_type_t 52 return RC; 174 T0, /* RC */ 201 B1, /* RC */
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/external/clang/test/SemaCXX/ |
H A D | nested-name-spec.cpp | 71 struct RC; 77 struct A2::RC { struct in class:A2 103 void f6(int A2::RC::x); // expected-error{{parameter declarator cannot be qualified}} 105 int A2::RC::x; // expected-error{{non-static data member defined out-of-line}}
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/external/harfbuzz_ng/src/ |
H A D | hb-ot-shape-complex-thai.cc | 40 RC, enumerator in enum:thai_consonant_type_t 52 return RC; 174 T0, /* RC */ 201 B1, /* RC */
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