Searched defs:Reg (Results 26 - 50 of 253) sorted by relevance

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/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp73 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); local
74 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
/external/llvm/lib/Target/ARM/
H A DARMCallingConv.h34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
49 if (unsigned Reg = State.AllocateReg(RegList, 4))
50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); local
80 if (Reg == 0) {
83 Reg = State.AllocateReg(GPRArgRegs, 4);
84 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
99 if (HiRegList[i] == Reg)
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); local
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/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp275 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); local
276 if (MRC.contains(Reg)) {
283 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
303 unsigned Reg = Op.getReg(); local
304 printRegName(O, Reg);
771 unsigned Reg = MI->getOperand(OpNum).getReg();
772 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
774 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
1064 unsigned Reg = MO1.getReg();
1065 printRegName(O, Reg);
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/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp57 void Hexagon_CCState::MarkAllocated(unsigned Reg) { argument
59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
101 unsigned Reg = Hexagon::R0; local
102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
107 unsigned Reg = Hexagon::D0; local
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
H A DHexagonCallingConvLower.h72 bool isAllocated(unsigned Reg) const {
73 return UsedRegs[Reg/32] & (1 << (Reg&31));
119 unsigned AllocateReg(unsigned Reg) { argument
120 if (isAllocated(Reg)) return 0;
121 MarkAllocated(Reg);
122 return Reg;
126 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
127 if (isAllocated(Reg)) return 0;
128 MarkAllocated(Reg);
142 unsigned Reg = Regs[FirstUnalloc]; local
155 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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H A DHexagonMachineFunctionInfo.h46 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp196 unsigned Reg = CSI[i-1].getReg(); local
198 MBB.addLiveIn(Reg);
200 .addReg(Reg, RegState::Kill);
/external/llvm/lib/Target/Mips/
H A DMips16FrameLowering.cpp68 unsigned Reg = I->getReg(); local
69 unsigned DReg = MRI->getDwarfRegNum(Reg, true);
122 unsigned Reg = CSI[i].getReg(); local
123 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
126 EntryBlock->addLiveIn(Reg);
H A DMipsMachineFunction.h62 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
85 int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; }
H A DMipsSERegisterInfo.cpp172 unsigned Reg = RegInfo.createVirtualRegister(RC); local
176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
178 FrameReg = Reg;
191 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, local
193 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
194 .addReg(Reg, RegState::Kill);
196 FrameReg = Reg;
/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp86 unsigned Reg = Op.getReg(); local
87 printRegName(O, Reg);
/external/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp89 unsigned Reg,
93 unsigned Reg,
130 /// This functions walks the use list of Reg until it finds an Instruction
136 unsigned Reg,
138 // The Reg parameter to the function must always be defined by either a PHI
140 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
141 "Reg cannot be a physical register");
143 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
146 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
162 unsigned Reg,
133 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
159 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
223 unsigned Reg = MI.getOperand(i).getReg(); local
228 unsigned Reg = MI.getOperand(0).getReg(); local
241 unsigned Reg = MI.getOperand(i).getReg(); local
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.cpp79 unsigned SystemZMC::getFirstReg(unsigned Reg) { argument
93 assert(Reg < SystemZ::NUM_TARGET_REGS);
94 return Map[Reg];
/external/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h35 void setLowSavedGPR(unsigned Reg) { LowSavedGPR = Reg; } argument
40 void setHighSavedGPR(unsigned Reg) { HighSavedGPR = Reg; } argument
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp128 unsigned Reg = MO.getReg(); local
129 if (!Reg)
131 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
170 unsigned Reg = isSub
173 if (Reg) {
178 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
299 unsigned Reg = II->first;
301 if (Reg == X86::EAX || Reg == X86::AX ||
302 Reg
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/external/llvm/tools/llvm-readobj/
H A DWin64EHDumper.cpp73 static StringRef getUnwindRegisterName(uint8_t Reg) { argument
74 switch (Reg) {
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp315 unsigned Reg, EVT VT) const {
319 if (!MRI.isLiveIn(Reg)) {
321 MRI.addLiveIn(Reg, VirtualRegister);
323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
H A DAMDGPUInstrInfo.cpp165 unsigned Reg, bool UnfoldLoad,
164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
H A DR600ISelLowering.cpp262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local
263 if (!MRI.isLiveOut(Reg)) {
264 MRI.addLiveOut(Reg);
266 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
H A DSIISelLowering.cpp367 unsigned Reg = dstClass->getRegister(SGPRIndex); local
369 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
/external/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h154 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { argument
155 if (!LiveOutRegInfo.inBounds(Reg))
158 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
170 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
173 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, argument
179 LiveOutRegInfo.grow(Reg);
180 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
198 unsigned Reg = It->second; local
199 LiveOutRegInfo.grow(Reg);
200 LiveOutRegInfo[Reg]
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H A DLiveIntervalAnalysis.h108 LiveInterval &getInterval(unsigned Reg) { argument
109 if (hasInterval(Reg))
110 return *VirtRegIntervals[Reg];
112 return createAndComputeVirtRegInterval(Reg);
115 const LiveInterval &getInterval(unsigned Reg) const {
116 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
119 bool hasInterval(unsigned Reg) const {
120 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
124 LiveInterval &createEmptyInterval(unsigned Reg) { argument
131 createAndComputeVirtRegInterval(unsigned Reg) argument
138 removeInterval(unsigned Reg) argument
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H A DScheduleDAGInstrs.h50 unsigned Reg; member in struct:llvm::PhysRegSUOper
52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
54 unsigned getSparseSetIndex() const { return Reg; }
H A DStackMaps.h91 unsigned Reg; member in struct:llvm::StackMaps::Location
93 Location() : LocType(Unprocessed), Size(0), Reg(0), Offset(0) {}
94 Location(LocationType LocType, unsigned Size, unsigned Reg, int64_t Offset) argument
95 : LocType(LocType), Size(Size), Reg(Reg), Offset(Offset) {}
99 unsigned short Reg; member in struct:llvm::StackMaps::LiveOutReg
103 LiveOutReg() : Reg(0), RegNo(0), Size(0) {}
104 LiveOutReg(unsigned short Reg, unsigned short RegNo, unsigned short Size) argument
105 : Reg(Reg), RegN
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/external/llvm/include/llvm/Support/
H A DARMWinEH.h40 /// | Stack Adjust |C|L|R| Reg |H|Ret| Function Length |Flg|
61 /// Reg : 3-bit field indicating the index of the last saved non-volatile
63 /// saved (r4-rN, where N is 4 + Reg). If the R bit is set to 1, then
65 /// 8 + Reg). The special case of the R bit being set to 1 and Reg equal
69 /// special case of the R-flag being set and Reg being set to 7 indicates
90 /// + r11 must NOT be included in the set of registers described by Reg
148 uint8_t Reg() const { function in class:llvm::ARM::WinEH::RuntimeFunction
172 assert(((~UnwindData & 0x00200000) || (Reg() < 7) || R()) &&
173 "r11 must not be included in Reg;
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