/external/llvm/lib/Target/Hexagon/InstPrinter/ |
H A D | HexagonInstPrinter.cpp | 41 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 43 printInst((const HexagonMCInst*)(MI), O, Annot); 46 void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O, argument 51 if (MI->getOpcode() == Hexagon::ENDLOOP0) { 53 assert(MI->isPacketEnd() && "Loop-end must also end the packet"); 55 if (MI->isPacketStart()) { 62 Nop.setPacketStart (MI->isPacketStart()); 67 if (MI->isPacketEnd()) 70 printInstruction(MI, O); 74 if (MI 89 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 104 printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 117 printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 125 printUnsignedImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 130 printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 135 printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 140 printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 149 printFrameIndexOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 157 printGlobalOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 164 printJumpTable(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 171 printConstantPool(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 178 printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 185 printCallOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 189 printAbsAddrOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 193 printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 197 printSymbol(const MCInst *MI, unsigned OpNo, raw_ostream &O, bool hi) const argument [all...] |
/external/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.cpp | 39 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 42 if (MI->getOpcode() == PPC::RLWINM) { 43 unsigned char SH = MI->getOperand(2).getImm(); 44 unsigned char MB = MI->getOperand(3).getImm(); 45 unsigned char ME = MI->getOperand(4).getImm(); 55 printOperand(MI, 0, O); 57 printOperand(MI, 1, O); 65 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && 66 MI 106 printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier) argument 203 printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 210 printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 217 printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 224 printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 231 printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 239 printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 247 printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 258 printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 267 printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 285 printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 296 printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 309 printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 337 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | AMDGPUInstrInfo.cpp | 40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument 47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument 53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, argument 59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, argument 65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, argument 70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, argument 75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, argument 107 MachineBasicBlock::iterator MI, 117 MachineBasicBlock::iterator MI, 124 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) cons 106 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 116 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 173 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument 181 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr *LoadMI) const argument 189 canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops) const argument 195 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 252 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument [all...] |
H A D | SILowerI1Copies.cpp | 85 MachineInstr &MI = *I; local 87 if (MI.getOpcode() == AMDGPU::V_MOV_I1) { 88 I1Defs.push_back(MI.getOperand(0).getReg()); 89 MI.setDesc(TII->get(AMDGPU::V_MOV_B32_e32)); 93 if (MI.getOpcode() == AMDGPU::V_AND_I1) { 94 I1Defs.push_back(MI.getOperand(0).getReg()); 95 MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32)); 99 if (MI.getOpcode() == AMDGPU::V_OR_I1) { 100 I1Defs.push_back(MI.getOperand(0).getReg()); 101 MI [all...] |
/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.h | 85 void printInstruction(const MCInst *MI, raw_ostream &O); 89 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; 91 bool printAliasInstr(const MCInst *MI, raw_ostream &OS); 92 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 96 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 97 void printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O); 98 void printUnsignedImm8(const MCInst *MI, int opNum, raw_ostream &O); 99 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); 100 void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O); 101 void printFCCOperand(const MCInst *MI, in [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitConst32AndConst64.cpp | 86 MachineInstr *MI = MII; local 87 int Opc = MI->getOpcode(); 89 int DestReg = MI->getOperand(0).getReg(); 90 MachineOperand &Symbol = MI->getOperand (1); 92 BuildMI (*MBB, MII, MI->getDebugLoc(), 94 BuildMI (*MBB, MII, MI->getDebugLoc(), 98 MII = MBB->erase (MI); 102 int DestReg = MI->getOperand(0).getReg(); 103 MachineOperand &Symbol = MI->getOperand (1); 105 BuildMI (*MBB, MII, MI [all...] |
H A D | HexagonInstrInfo.h | 50 unsigned isLoadFromStackSlot(const MachineInstr *MI, 58 unsigned isStoreToStackSlot(const MachineInstr *MI, 74 bool analyzeCompare(const MachineInstr *MI, 106 MachineInstr* MI, 111 MachineInstr* MI, 119 bool isBranch(const MachineInstr *MI) const; 120 bool isPredicable(MachineInstr *MI) const override; 121 bool PredicateInstruction(MachineInstr *MI, 134 bool isPredicated(const MachineInstr *MI) const override; 136 bool isPredicatedTrue(const MachineInstr *MI) cons [all...] |
H A D | HexagonVLIWPacketizer.cpp | 128 bool ignorePseudoInstruction(MachineInstr *MI, 131 // isSoloInstruction - return true if instruction MI can not be packetized 132 // with any other instruction, which means that MI itself is a packet. 133 bool isSoloInstruction(MachineInstr *MI) override; 143 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override; 145 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg); 146 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, 149 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU, 154 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU, 158 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInst 218 MachineBasicBlock::iterator MI = MBB->begin(); local 268 IsIndirectCall(MachineInstr* MI) argument 275 reserveResourcesForConstExt(MachineInstr* MI) argument 291 canReserveResourcesForConstExt(MachineInstr *MI) argument 305 tryAllocateResourcesForConstExt(MachineInstr* MI) argument 322 IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg) argument 370 IsDirectJump(MachineInstr* MI) argument 374 IsSchedBarrier(MachineInstr* MI) argument 382 IsControlFlow(MachineInstr* MI) argument 386 IsLoopN(MachineInstr *MI) argument 393 DoesModifyCalleeSavedReg(MachineInstr *MI, const TargetRegisterInfo *TRI) argument 405 isNewifiable(MachineInstr* MI) argument 413 isCondInst(MachineInstr* MI) argument 432 PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument 449 DemoteToDotOld(MachineInstr* MI) argument 464 getPredicateSense(MachineInstr* MI, const HexagonInstrInfo *QII) argument 475 GetPostIncrementOperand(MachineInstr *MI, const HexagonInstrInfo *QII) argument 515 GetStoreValueOperand(MachineInstr *MI) argument 539 CanPromoteToNewValueStore( MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit) argument 720 CanPromoteToNewValue( MachineInstr *MI, SUnit *PacketSU, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit, MachineBasicBlock::iterator &MII) argument 749 CanPromoteToDotNew( MachineInstr *MI, SUnit *PacketSU, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC ) argument 806 RestrictingDepExistInPacket(MachineInstr* MI, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit) argument 842 getPredicatedRegister(MachineInstr *MI, const HexagonInstrInfo *QII) argument 957 ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) argument 978 isSoloInstruction(MachineInstr *MI) argument 1352 addToPacket(MachineInstr *MI) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 28 uint64_t getBinaryCodeForInstr(const MCInst &MI, 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument 36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, argument 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, argument 44 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const { argument 47 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, argument 51 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, argument
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/external/llvm/lib/CodeGen/ |
H A D | AntiDepBreaker.h | 54 virtual void Observe(MachineInstr *MI, unsigned Count, 62 void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) { argument 63 assert (MI->isDebugValue() && "MI is not DBG_VALUE!"); 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg) 65 MI->getOperand(0).setReg(NewReg);
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 28 uint64_t getBinaryCodeForInstr(const MCInst &MI, 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument 36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, argument 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, argument 44 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const { argument 47 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, argument 51 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, argument
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZAsmPrinter.cpp | 29 // Return an RI instruction like MI with opcode Opcode, but with the 31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { argument 32 if (MI->isCompare()) 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 35 .addImm(MI->getOperand(1).getImm()); 38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) 40 .addImm(MI->getOperand(2).getImm()); 43 // Return an RI instruction like MI with opcode Opcode, but with the 45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigne argument 59 lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) argument 69 EmitInstruction(const MachineInstr *MI) argument 193 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) argument 210 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) argument [all...] |
H A D | SystemZInstrInfo.cpp | 48 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores, 50 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI, argument 52 MachineBasicBlock *MBB = MI->getParent(); 57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI); 58 MBB->insert(MI, EarlierMI); 62 MachineOperand &LowRegOp = MI->getOperand(0); 69 MachineOperand &LowOffsetOp = MI->getOperand(2); 78 MI->setDesc(get(LowOpcode)); 81 // Split ADJDYNALLOC instruction MI. 82 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) cons 103 expandRIPseudo(MachineInstr *MI, unsigned LowOpcode, unsigned HighOpcode, bool ConvertHigh) const argument 117 expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode, unsigned LowOpcodeK, unsigned HighOpcode) const argument 138 expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode, unsigned HighOpcode) const argument 149 expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode, unsigned Size) const argument 193 isSimpleMove(const MachineInstr *MI, int &FrameIndex, unsigned Flag) argument 206 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const argument 211 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument 216 isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, int &SrcFrameIndex) const argument 399 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument 426 isShift(MachineInstr *MI, int Opcode, int64_t Imm) argument 433 eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) argument 467 MachineInstr *MI = MBBI; local 533 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument 623 isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) argument 677 MachineInstr *MI = MBBI; local 747 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument 865 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr* LoadMI) const argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.h | 51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 54 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 55 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 57 bool hasLoadFromStackSlot(const MachineInstr *MI, 60 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 61 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, 63 bool hasStoreFromStackSlot(const MachineInstr *MI, 74 MachineBasicBlock::iterator MI, DebugLoc DL, 79 MachineBasicBlock::iterator MI, 84 MachineBasicBlock::iterator MI, [all...] |
H A D | AMDGPUMCInstLower.cpp | 30 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument 31 OutMI.setOpcode(MI->getOpcode()); 33 for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) { 34 const MachineOperand &MO = MI->getOperand(i); 58 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument 62 if (MI->getOpcode() == AMDGPU::MASK_WRITE) { 66 if (MI->isBundle()) { 67 const MachineBasicBlock *MBB = MI->getParent(); 68 MachineBasicBlock::const_instr_iterator I = MI; 79 MCInstLowering.lower(MI, TmpIns [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.h | 51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 54 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 55 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 57 bool hasLoadFromStackSlot(const MachineInstr *MI, 60 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 61 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, 63 bool hasStoreFromStackSlot(const MachineInstr *MI, 74 MachineBasicBlock::iterator MI, DebugLoc DL, 79 MachineBasicBlock::iterator MI, 84 MachineBasicBlock::iterator MI, [all...] |
H A D | AMDGPUMCInstLower.cpp | 30 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument 31 OutMI.setOpcode(MI->getOpcode()); 33 for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) { 34 const MachineOperand &MO = MI->getOperand(i); 58 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument 62 if (MI->getOpcode() == AMDGPU::MASK_WRITE) { 66 if (MI->isBundle()) { 67 const MachineBasicBlock *MBB = MI->getParent(); 68 MachineBasicBlock::const_instr_iterator I = MI; 79 MCInstLowering.lower(MI, TmpIns [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 60 unsigned getMachineOpValue(const MachineInstr &MI, 63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const; 64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 66 unsigned getAbsDirectBrEncoding(const MachineInstr &MI, 68 unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 70 unsigned getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const; 71 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const; 72 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigne 120 const MachineInstr &MI = *I; local 145 get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const argument 187 getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const argument 196 getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const argument 203 getAbsDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const argument 211 getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const argument 216 getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const argument 232 getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const argument 248 getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const argument 264 getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const argument 270 getTLSCallEncoding(const MachineInstr &MI, unsigned OpNo) const argument 276 getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const argument [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 49 void printOperand(const MachineInstr *MI, int OpNum, 51 void printSrcMemOperand(const MachineInstr *MI, int OpNum, 53 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 56 bool PrintAsmMemoryOperand(const MachineInstr *MI, 59 void EmitInstruction(const MachineInstr *MI) override; 64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument 66 const MachineOperand &MO = MI->getOperand(OpNum); 105 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, argument 107 const MachineOperand &Base = MI->getOperand(OpNum); 108 const MachineOperand &Disp = MI 127 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 138 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 150 EmitInstruction(const MachineInstr *MI) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument 22 const MCInstrDesc &MCID = MI->getDesc(); 24 if (MI->mayStore()) 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 38 MachineInstr *MI = SU->getInstr(); local 40 if (!MI->isDebugValue()) { 43 const MCInstrDesc &MCID = MI->getDesc(); 48 MI->getParent()->getParent()->getTarget(); 66 (TII.canCauseFpMLxStall(MI->getOpcode()) || 67 hasRAWHazard(DefMI, MI, TI 86 MachineInstr *MI = SU->getInstr(); local [all...] |
H A D | A15SDOptimizer.cpp | 59 bool runOnInstruction(MachineInstr *MI); 99 bool hasPartialWrite(MachineInstr *MI); 100 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI); 107 MachineInstr *elideCopies(MachineInstr *MI); 108 void elideCopiesAndPHIs(MachineInstr *MI, 114 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg); 115 unsigned optimizeSDPattern(MachineInstr *MI); 121 void eraseInstrWithNoUses(MachineInstr *MI); 158 MachineInstr *MI = MRI->getVRegDef(SReg); 159 if (!MI) retur 179 eraseInstrWithNoUses(MachineInstr *MI) argument 247 optimizeSDPattern(MachineInstr *MI) argument 329 hasPartialWrite(MachineInstr *MI) argument 347 elideCopies(MachineInstr *MI) argument 360 elideCopiesAndPHIs(MachineInstr *MI, SmallVectorImpl<MachineInstr*> &Outs) argument 402 getReadDPRs(MachineInstr *MI) argument 528 optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) argument 583 runOnInstruction(MachineInstr *MI) argument 634 MachineInstr *MI = *II; local [all...] |
/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 49 uint64_t getBinaryCodeForInstr(const MCInst &MI, 55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 63 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, 69 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 75 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, 81 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 87 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, 94 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, 100 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 106 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigne 216 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 227 getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 248 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 274 getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 301 getCondBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 323 getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 343 getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 352 getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 371 getTestBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 393 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 421 getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 445 getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 453 getSIMDShift64_32OpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 462 getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 471 getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 481 getFixedPointScaleOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 490 getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 499 getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 508 getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 517 getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 526 getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 535 getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 544 getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 553 getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 563 getMoveVecShifterOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 574 fixMOVZ(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument 605 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 623 fixMulHigh(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument 633 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument 642 fixOneOperandFPComparison( const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 76 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 78 unsigned Opcode = MI->getOpcode(); 86 switch (MI->getOperand(0).getImm()) { 99 printInstruction(MI, O); 103 printPredicateOperand(MI, 1, O); 112 const MCOperand &Dst = MI->getOperand(0); 113 const MCOperand &MO1 = MI->getOperand(1); 114 const MCOperand &MO2 = MI->getOperand(2); 115 const MCOperand &MO3 = MI->getOperand(3); 118 printSBitModifierOperand(MI, 299 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 339 printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | LiveVariables.h | 94 bool removeKill(MachineInstr *MI) { argument 96 I = std::find(Kills.begin(), Kills.end(), MI); 146 // DistanceMap - Keep track the distance of a MI from the start of the 153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI); 158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); 159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI, 161 void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs); 184 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const; 198 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI, argument 200 if (MI 208 removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) argument 234 addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI, bool AddIfNotFound = false) argument 244 removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) argument [all...] |
/external/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.h | 28 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; 31 void printInstruction(const MCInst *MI, raw_ostream &O); 34 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, 36 void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 37 void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, 39 void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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