Searched refs:rt (Results 26 - 50 of 414) sorted by relevance

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/external/valgrind/main/none/tests/mips32/
H A DMoveIns.stdout.exp2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
10 mfc1 $v1, $f8 :: fs nan, rt 0xffffffff
11 mfc1 $s0, $f9 :: fs nan, rt
[all...]
/external/chromium_org/v8/src/mips64/
H A Dassembler-mips64.h627 void beq(Register rs, Register rt, int16_t offset);
628 void beq(Register rs, Register rt, Label* L) { argument
629 beq(rs, rt, branch_offset(L, false) >> 2);
632 void bgezc(Register rt, int16_t offset);
633 void bgezc(Register rt, Label* L) { argument
634 bgezc(rt, branch_offset_compact(L, false)>>2);
636 void bgeuc(Register rs, Register rt, int16_t offset);
637 void bgeuc(Register rs, Register rt, Label* L) { argument
638 bgeuc(rs, rt, branch_offset_compact(L, false)>>2);
640 void bgec(Register rs, Register rt, int16_
641 bgec(Register rs, Register rt, Label* L) argument
646 bgezalc(Register rt, Label* L) argument
655 bgtzc(Register rt, Label* L) argument
660 blezc(Register rt, Label* L) argument
665 bltzc(Register rt, Label* L) argument
669 bltuc(Register rs, Register rt, Label* L) argument
673 bltc(Register rs, Register rt, Label* L) argument
679 blezalc(Register rt, Label* L) argument
683 bltzalc(Register rt, Label* L) argument
687 bgtzalc(Register rt, Label* L) argument
691 beqzalc(Register rt, Label* L) argument
695 beqc(Register rs, Register rt, Label* L) argument
703 bnezalc(Register rt, Label* L) argument
707 bnec(Register rs, Register rt, Label* L) argument
711 bnezc(Register rt, Label* L) argument
715 bne(Register rs, Register rt, Label* L) argument
719 bovc(Register rs, Register rt, Label* L) argument
723 bnvc(Register rs, Register rt, Label* L) argument
[all...]
H A Dassembler-mips64.cc336 Register rt; local
337 rt.code_ = (instr & kRtFieldMask) >> kRtShift;
338 return rt;
563 uint32_t rt = GetRt(instr);
575 rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) &&
852 Register rt,
856 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
857 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
865 Register rt,
869 DCHECK(rs.is_valid() && rt
850 GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, uint16_t sa, SecondaryField func) argument
863 GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, uint16_t lsb, SecondaryField func) argument
902 GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, FPURegister fs, FPURegister fd, SecondaryField func) argument
915 GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, FPUControlRegister fs, SecondaryField func) argument
929 GenInstrImmediate(Opcode opcode, Register rs, Register rt, int32_t j) argument
1153 beq(Register rs, Register rt, int16_t offset) argument
1167 bgezc(Register rt, int16_t offset) argument
1174 bgeuc(Register rs, Register rt, int16_t offset) argument
1183 bgec(Register rs, Register rt, int16_t offset) argument
1208 bgtzc(Register rt, int16_t offset) argument
1222 blezc(Register rt, int16_t offset) argument
1229 bltzc(Register rt, int16_t offset) argument
1236 bltuc(Register rs, Register rt, int16_t offset) argument
1245 bltc(Register rs, Register rt, int16_t offset) argument
1270 bne(Register rs, Register rt, int16_t offset) argument
1277 bovc(Register rs, Register rt, int16_t offset) argument
1285 bnvc(Register rs, Register rt, int16_t offset) argument
1293 blezalc(Register rt, int16_t offset) argument
1300 bgezalc(Register rt, int16_t offset) argument
1314 bltzalc(Register rt, int16_t offset) argument
1321 bgtzalc(Register rt, int16_t offset) argument
1328 beqzalc(Register rt, int16_t offset) argument
1335 bnezalc(Register rt, int16_t offset) argument
1342 beqc(Register rs, Register rt, int16_t offset) argument
1357 bnec(Register rs, Register rt, int16_t offset) argument
1449 addu(Register rd, Register rs, Register rt) argument
1459 subu(Register rd, Register rs, Register rt) argument
1464 mul(Register rd, Register rs, Register rt) argument
1473 muh(Register rd, Register rs, Register rt) argument
1479 mulu(Register rd, Register rs, Register rt) argument
1485 muhu(Register rd, Register rs, Register rt) argument
1491 dmul(Register rd, Register rs, Register rt) argument
1497 dmuh(Register rd, Register rs, Register rt) argument
1503 dmulu(Register rd, Register rs, Register rt) argument
1509 dmuhu(Register rd, Register rs, Register rt) argument
1515 mult(Register rs, Register rt) argument
1521 multu(Register rs, Register rt) argument
1532 div(Register rs, Register rt) argument
1537 div(Register rd, Register rs, Register rt) argument
1543 mod(Register rd, Register rs, Register rt) argument
1549 divu(Register rs, Register rt) argument
1554 divu(Register rd, Register rs, Register rt) argument
1560 modu(Register rd, Register rs, Register rt) argument
1566 daddu(Register rd, Register rs, Register rt) argument
1571 dsubu(Register rd, Register rs, Register rt) argument
1576 dmult(Register rs, Register rt) argument
1581 dmultu(Register rs, Register rt) argument
1586 ddiv(Register rs, Register rt) argument
1591 ddiv(Register rd, Register rs, Register rt) argument
1597 dmod(Register rd, Register rs, Register rt) argument
1603 ddivu(Register rs, Register rt) argument
1608 ddivu(Register rd, Register rs, Register rt) argument
1614 dmodu(Register rd, Register rs, Register rt) argument
1622 and_(Register rd, Register rs, Register rt) argument
1627 andi(Register rt, Register rs, int32_t j) argument
1633 or_(Register rd, Register rs, Register rt) argument
1638 ori(Register rt, Register rs, int32_t j) argument
1644 xor_(Register rd, Register rs, Register rt) argument
1649 xori(Register rt, Register rs, int32_t j) argument
1655 nor(Register rd, Register rs, Register rt) argument
1661 sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop) argument
1674 sllv(Register rd, Register rt, Register rs) argument
1679 srl(Register rd, Register rt, uint16_t sa) argument
1684 srlv(Register rd, Register rt, Register rs) argument
1689 sra(Register rd, Register rt, uint16_t sa) argument
1694 srav(Register rd, Register rt, Register rs) argument
1699 rotr(Register rd, Register rt, uint16_t sa) argument
1709 rotrv(Register rd, Register rt, Register rs) argument
1719 dsll(Register rd, Register rt, uint16_t sa) argument
1724 dsllv(Register rd, Register rt, Register rs) argument
1729 dsrl(Register rd, Register rt, uint16_t sa) argument
1734 dsrlv(Register rd, Register rt, Register rs) argument
1739 drotr(Register rd, Register rt, uint16_t sa) argument
1747 drotrv(Register rd, Register rt, Register rs) argument
1755 dsra(Register rd, Register rt, uint16_t sa) argument
1760 dsrav(Register rd, Register rt, Register rs) argument
1765 dsll32(Register rd, Register rt, uint16_t sa) argument
1770 dsrl32(Register rd, Register rt, uint16_t sa) argument
1775 dsra32(Register rd, Register rt, uint16_t sa) argument
1909 aui(Register rs, Register rt, int32_t j) argument
1917 daui(Register rs, Register rt, int32_t j) argument
2009 tge(Register rs, Register rt, uint16_t code) argument
2017 tgeu(Register rs, Register rt, uint16_t code) argument
2025 tlt(Register rs, Register rt, uint16_t code) argument
2033 tltu(Register rs, Register rt, uint16_t code) argument
2042 teq(Register rs, Register rt, uint16_t code) argument
2050 tne(Register rs, Register rt, uint16_t code) argument
2071 slt(Register rd, Register rs, Register rt) argument
2076 sltu(Register rd, Register rs, Register rt) argument
2081 slti(Register rt, Register rs, int32_t j) argument
2086 sltiu(Register rt, Register rs, int32_t j) argument
2092 movz(Register rd, Register rs, Register rt) argument
2097 movn(Register rd, Register rs, Register rt) argument
2103 Register rt; local
2110 Register rt; local
2129 seleqz(Register rs, Register rt, Register rd) argument
2149 selnez(Register rs, Register rt, Register rd) argument
2179 ins_(Register rt, Register rs, uint16_t pos, uint16_t size) argument
2187 ext_(Register rt, Register rs, uint16_t pos, uint16_t size) argument
2226 mtc1(Register rt, FPURegister fs) argument
2231 mthc1(Register rt, FPURegister fs) argument
2236 dmtc1(Register rt, FPURegister fs) argument
2241 mfc1(Register rt, FPURegister fs) argument
2246 mfhc1(Register rt, FPURegister fs) argument
2251 dmfc1(Register rt, FPURegister fs) argument
2256 ctc1(Register rt, FPUControlRegister fs) argument
2261 cfc1(Register rt, FPUControlRegister fs) argument
[all...]
/external/dhcpcd/
H A Dif-linux.c234 struct rt rt; local
253 rt.iface = NULL;
254 rt.dest.s_addr = INADDR_ANY;
255 rt.net.s_addr = INADDR_ANY;
256 rt.gate.s_addr = INADDR_ANY;
257 rt.next = NULL;
262 memcpy(&rt.dest.s_addr, RTA_DATA(rta),
263 sizeof(rt.dest.s_addr));
266 memcpy(&rt
488 struct rtmsg rt; member in struct:nlmr
531 if_route(const struct rt *rt, int action) argument
[all...]
H A Dif-bsd.c190 if_route(const struct rt *rt, int action) argument
234 if (rt->gate.s_addr != INADDR_ANY ||
235 rt->net.s_addr != rt->iface->net.s_addr ||
236 rt->dest.s_addr != (rt->iface->addr.s_addr & rt->iface->net.s_addr))
239 if (rt->dest.s_addr == rt
321 struct rt rt; local
[all...]
/external/chromium_org/tools/memory_inspector/memory_inspector/classification/
H A Drules_unittest.py62 rt = rules.Load(_TEST_RULE, MockRule)
63 self.assertEqual(rt.name, 'Total')
64 self.assertEqual(len(rt.children), 3)
65 node1 = rt.children[0]
66 node2 = rt.children[1]
67 node3 = rt.children[2]
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/builderTemplate/componentScripts/
H A Dbuild.properties15 # bootclasspath - The base jars to compile against (typicaly rt.jar)
108 # The location of the Java jars to compile against. Typically the rt.jar for your JDK/JRE
109 bootclasspath=d:/ibm1.3.1/jre/lib/rt.jar
/external/chromium_org/v8/src/mips/
H A Ddisasm-mips.cc305 } else if (format[1] == 't') { // 'rt: rt register.
460 Format(instr, "mfc1 'rt, 'fs");
463 Format(instr, "mfhc1 'rt, 'fs");
466 Format(instr, "mtc1 'rt, 'fs");
470 Format(instr, "ctc1 'rt, 'fs");
473 Format(instr, "cfc1 'rt, 'fs");
476 Format(instr, "mthc1 'rt, 'fs");
642 Format(instr, "sll 'rd, 'rt, 'sa");
646 Format(instr, "srl 'rd, 'rt, 's
[all...]
/external/chromium_org/ui/gfx/geometry/
H A Dr_tree_unittest.cc18 void ValidateRTree(RTreeBase* rt) { argument
20 if (!rt->root()->count()) {
21 EXPECT_TRUE(rt->root()->rect().IsEmpty());
22 EXPECT_EQ(0, rt->root()->Level());
27 EXPECT_LE(rt->root()->count(), rt->max_children_);
29 EXPECT_GT(rt->root()->Level(), -1);
31 EXPECT_TRUE(rt->root()->parent() == NULL);
33 CheckBoundsConsistent(rt->root());
34 for (size_t i = 0; i < rt
71 AddStackedSquares(RT* rt, int count) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/llvmpipe/
H A Dlp_bld_blend_soa.c201 * \param rt render target index (to index the blend / colormask state)
211 unsigned rt,
221 assert(rt < PIPE_MAX_COLOR_BUFS);
234 if (blend->rt[rt].colormask & (1 << i)) {
242 else if (blend->rt[rt].blend_enable) {
243 unsigned src_factor = i < 3 ? blend->rt[rt].rgb_src_factor : blend->rt[r
208 lp_build_blend_soa(struct gallivm_state *gallivm, const struct pipe_blend_state *blend, struct lp_type type, unsigned rt, LLVMValueRef src[4], LLVMValueRef dst[4], LLVMValueRef con[4], LLVMValueRef res[4]) argument
[all...]
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_bld_blend_soa.c201 * \param rt render target index (to index the blend / colormask state)
211 unsigned rt,
221 assert(rt < PIPE_MAX_COLOR_BUFS);
234 if (blend->rt[rt].colormask & (1 << i)) {
242 else if (blend->rt[rt].blend_enable) {
243 unsigned src_factor = i < 3 ? blend->rt[rt].rgb_src_factor : blend->rt[r
208 lp_build_blend_soa(struct gallivm_state *gallivm, const struct pipe_blend_state *blend, struct lp_type type, unsigned rt, LLVMValueRef src[4], LLVMValueRef dst[4], LLVMValueRef con[4], LLVMValueRef res[4]) argument
[all...]
/external/compiler-rt/test/builtins/Unit/
H A Dumodti3_test.c32 utwords rt; local
33 rt.all = r;
38 at.s.high, at.s.low, bt.s.high, bt.s.low, rt.s.high, rt.s.low,
/external/emma/core/java12/com/vladium/emma/rt/
H A DClassPathCacheEntry.java9 package com.vladium.emma.rt;
/external/skia/bench/
H A DDeferredSurfaceCopyBench.cpp46 GrRenderTarget* rt = reinterpret_cast<GrRenderTarget*>( variable
48 if (NULL != rt) {
49 surface = SkSurface::NewRenderTarget(rt->getContext(), info, rt->numSamples());
/external/deqp/modules/gles2/
H A Dtes2InfoTests.cpp102 const tcu::RenderTarget& rt = m_context.getRenderTarget(); local
103 const tcu::PixelFormat& pf = rt.getPixelFormat();
110 << tcu::TestLog::Integer("DepthBits", "Depth bits", "", QP_KEY_TAG_NONE, rt.getDepthBits())
111 << tcu::TestLog::Integer("StencilBits", "Stencil bits", "", QP_KEY_TAG_NONE, rt.getStencilBits())
112 << tcu::TestLog::Integer("NumSamples", "Number of samples", "", QP_KEY_TAG_NONE, rt.getNumSamples())
113 << tcu::TestLog::Integer("Width", "Width", "", QP_KEY_TAG_NONE, rt.getWidth())
114 << tcu::TestLog::Integer("Height", "Height", "", QP_KEY_TAG_NONE, rt.getHeight());
/external/deqp/modules/gles3/
H A Dtes3InfoTests.cpp102 const tcu::RenderTarget& rt = m_context.getRenderTarget(); local
103 const tcu::PixelFormat& pf = rt.getPixelFormat();
110 << tcu::TestLog::Integer("DepthBits", "Depth bits", "", QP_KEY_TAG_NONE, rt.getDepthBits())
111 << tcu::TestLog::Integer("StencilBits", "Stencil bits", "", QP_KEY_TAG_NONE, rt.getStencilBits())
112 << tcu::TestLog::Integer("NumSamples", "Number of samples", "", QP_KEY_TAG_NONE, rt.getNumSamples())
113 << tcu::TestLog::Integer("Width", "Width", "", QP_KEY_TAG_NONE, rt.getWidth())
114 << tcu::TestLog::Integer("Height", "Height", "", QP_KEY_TAG_NONE, rt.getHeight());
/external/deqp/modules/gles31/
H A Dtes31InfoTests.cpp102 const tcu::RenderTarget& rt = m_context.getRenderTarget(); local
103 const tcu::PixelFormat& pf = rt.getPixelFormat();
110 << tcu::TestLog::Integer("DepthBits", "Depth bits", "", QP_KEY_TAG_NONE, rt.getDepthBits())
111 << tcu::TestLog::Integer("StencilBits", "Stencil bits", "", QP_KEY_TAG_NONE, rt.getStencilBits())
112 << tcu::TestLog::Integer("NumSamples", "Number of samples", "", QP_KEY_TAG_NONE, rt.getNumSamples())
113 << tcu::TestLog::Integer("Width", "Width", "", QP_KEY_TAG_NONE, rt.getWidth())
114 << tcu::TestLog::Integer("Height", "Height", "", QP_KEY_TAG_NONE, rt.getHeight());
/external/chromium_org/chrome/browser/component_updater/
H A Dcomponent_updater_resource_throttle.cc81 void UnblockThrottleOnUIThread(base::WeakPtr<CUResourceThrottle> rt) { argument
84 base::Bind(&CUResourceThrottle::Unblock, rt));
97 CUResourceThrottle* rt = new CUResourceThrottle; local
104 base::Bind(&UnblockThrottleOnUIThread, rt->AsWeakPtr())));
105 return rt;
/external/chromium_org/gpu/config/
H A Dgpu_util.cc25 std::string rt; local
28 if (!rt.empty())
29 rt += ",";
30 rt += base::IntToString(*it);
32 return rt;
/external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/
H A Dst_atom_blend.c156 * Figure out if colormasks are different per rt.
172 * Figure out if blend enables/state are different per rt.
212 blend->rt[i].blend_enable = (ctx->Color.BlendEnabled >> i) & 0x1;
217 blend->rt[i].rgb_func =
223 blend->rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ONE;
224 blend->rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ONE;
227 blend->rt[i].rgb_src_factor =
229 blend->rt[i].rgb_dst_factor =
233 blend->rt[i].alpha_func =
239 blend->rt[
[all...]
/external/mesa3d/src/mesa/state_tracker/
H A Dst_atom_blend.c156 * Figure out if colormasks are different per rt.
172 * Figure out if blend enables/state are different per rt.
212 blend->rt[i].blend_enable = (ctx->Color.BlendEnabled >> i) & 0x1;
217 blend->rt[i].rgb_func =
223 blend->rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ONE;
224 blend->rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ONE;
227 blend->rt[i].rgb_src_factor =
229 blend->rt[i].rgb_dst_factor =
233 blend->rt[i].alpha_func =
239 blend->rt[
[all...]
/external/chromium_org/third_party/WebKit/Source/core/rendering/
H A DRenderRubyRun.cpp203 RenderRubyText* rt = rubyText(); local
204 if (!rt)
207 layoutScope.setChildNeedsLayout(rt);
208 rt->layoutIfNeeded();
209 return rt;
216 RenderRubyText* rt = rubyText(); local
217 if (!rt)
220 rt->setLogicalLeft(0);
223 LayoutUnit lastLineRubyTextBottom = rt->logicalHeight();
225 RootInlineBox* rootBox = rt
[all...]
/external/compiler-rt/
H A DAndroid.mk222 define get-libcompiler-rt-source-files
223 $(if $(findstring $(1),arm),$(call get-libcompiler-rt-arm-source-files),
224 $(if $(findstring $(1),mips),$(call get-libcompiler-rt-mips-source-files),
225 $(if $(findstring $(1),x86),$(call get-libcompiler-rt-x86-source-files),
226 $(if $(findstring $(1),x86_64),$(call get-libcompiler-rt-x86_64-source-files),
227 $(if $(findstring $(1),x32),$(call get-libcompiler-rt-x86-source-files),
228 $(if $(findstring $(1),arm64),$(call get-libcompiler-rt-arm64-source-files),
229 $(if $(findstring $(1),mips64),$(call get-libcompiler-rt-mips64-source-files),
239 define filter-libcompiler-rt-common-source-files
246 define get-libcompiler-rt
[all...]
/external/pdfium/core/include/fxcrt/
H A Dfx_coordinates.h311 void Inflate(const FXT_RECT &rt) argument
313 Inflate(rt.left, rt.top, rt.left + rt.width, rt.top + rt.height);
333 void Deflate(const FXT_RECT &rt) argument
335 Deflate(rt.left, rt
462 Union(const FXT_RECT &rt) argument
480 Intersect(const FXT_RECT &rt) argument
504 IntersectWith(const FXT_RECT &rt, FX_FLOAT fEpsilon) const argument
700 Inflate(const CFX_FloatRect &rt) argument
723 Deflate(const CFX_FloatRect &rt) argument
[all...]
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/builderTemplate/tests/
H A Dbuild.properties25 bootclasspath=${java.home}/lib/rt.jar

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