Searched refs:MI (Results 251 - 275 of 514) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h154 void Observe(MachineInstr *MI, unsigned Count,
165 /// that is both implicitly used and defined in MI
166 bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO);
168 /// GetPassthruRegs - If MI implicitly def/uses a register, then
170 void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
176 void PrescanInstruction(MachineInstr *MI, unsigned Count,
178 void ScanInstruction(MachineInstr *MI, unsigned Count);
H A DTailDuplication.cpp90 void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB,
96 void DuplicateInstruction(MachineInstr *MI,
166 MachineBasicBlock::iterator MI = MBB->begin(); local
167 while (MI != MBB->end()) {
168 if (!MI->isPHI())
174 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
175 MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB();
182 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
189 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
190 MachineBasicBlock *PHIBB = MI
354 getPHISrcRegOpIdx(MachineInstr *MI, MachineBasicBlock *SrcBB) argument
395 ProcessPHI( MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB, DenseMap<unsigned, unsigned> &LocalVRMap, SmallVectorImpl<std::pair<unsigned, unsigned> > &Copies, const DenseSet<unsigned> &RegsUsedByPhi, bool Remove) argument
426 DuplicateInstruction(MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB, MachineFunction &MF, DenseMap<unsigned, unsigned> &LocalVRMap, const DenseSet<unsigned> &UsedByPhi) argument
820 MachineInstr *MI = &*I; local
878 MachineInstr *MI = &*I++; local
888 MachineInstr *MI = &*I++; local
951 MachineInstr *MI = &*I++; local
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H A DVirtRegMap.cpp293 MachineInstr *MI = MII; local
301 if (!HasUWTable && IsExitBB && MI->isCall()) {
302 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
303 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
314 NoReturnInsts.insert(MI);
319 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
320 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
379 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
382 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
385 MI
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H A DScheduleDAGInstrs.cpp47 cl::desc("Enable use of AA during MI GAD construction"));
50 cl::init(true), cl::desc("Enable use of TBAA during MI GAD construction"));
135 static void getUnderlyingObjectsForInstr(const MachineInstr *MI, argument
138 if (!MI->hasOneMemOperand() ||
139 (!(*MI->memoperands_begin())->getValue() &&
140 !(*MI->memoperands_begin())->getPseudoValue()) ||
141 (*MI->memoperands_begin())->isVolatile())
145 (*MI->memoperands_begin())->getPseudoValue()) {
156 const Value *V = (*MI->memoperands_begin())->getValue();
296 MachineInstr *MI local
377 const MachineInstr *MI = SU->getInstr(); local
415 MachineInstr *MI = SU->getInstr(); local
462 isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) argument
472 isUnsafeMemoryObject(MachineInstr *MI, const MachineFrameInfo *MFI) argument
690 MachineInstr *MI = I; local
788 MachineInstr *MI = std::prev(MII); local
1073 toggleKillFlag(MachineInstr *MI, MachineOperand &MO) argument
1117 MachineInstr *MI = --I; local
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H A DRegAllocBase.cpp114 MachineInstr *MI = nullptr; local
120 MI = TmpMI;
124 if (MI)
125 MI->emitError("inline assembly requires more registers than available");
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, argument
37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43 if (MI
66 getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) argument
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/external/llvm/lib/Target/MSP430/
H A DMSP430MCInstLower.cpp113 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { argument
114 OutMI.setOpcode(MI->getOpcode());
116 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
117 const MachineOperand &MO = MI->getOperand(i);
122 MI->dump();
H A DMSP430RegisterInfo.cpp109 MachineInstr &MI = *II; local
110 MachineBasicBlock &MBB = *MI.getParent();
113 DebugLoc dl = MI.getDebugLoc();
114 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
128 Offset += MI.getOperand(FIOperandNum + 1).getImm();
130 if (MI.getOpcode() == MSP430::ADD16ri) {
136 MI.setDesc(TII.get(MSP430::MOV16rr));
137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
143 unsigned DstReg = MI.getOperand(0).getReg();
154 MI
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H A DMSP430FrameLowering.cpp97 MachineInstr *MI = local
101 MI->getOperand(3).setIsDead();
159 MachineInstr *MI = local
164 MI->getOperand(3).setIsDead();
169 MachineInstr *MI = local
173 MI->getOperand(3).setIsDead();
181 MachineBasicBlock::iterator MI,
188 if (MI != MBB.end()) DL = MI->getDebugLoc();
199 BuildMI(MBB, MI, D
180 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
206 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/R600/
H A DR600MachineScheduler.cpp183 isPhysicalRegCopy(MachineInstr *MI) { argument
184 if (MI->getOpcode() != AMDGPU::COPY)
187 return !TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg());
221 MachineInstr *MI = SU->getInstr(); local
223 if (TII->isTransOnly(MI))
226 switch (MI->getOpcode()) {
235 if (MI->getOperand(1).isUndef()) {
236 // MI will become a KILL, don't considers it in scheduling
246 if(TII->isVector(*MI) ||
247 TII->isCubeOp(MI
357 AssignSlot(MachineInstr* MI, unsigned Slot) argument
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H A DSIFixSGPRLiveRanges.cpp86 MachineInstr &MI = *I; local
87 MachineOperand *ExecUse = MI.findRegisterUseOperand(AMDGPU::EXEC);
91 for (const MachineOperand &Def : MI.operands()) {
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp37 unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
38 const MachineBasicBlock &MBB = *MI->getParent();
42 if (MI->getOpcode() == AArch64::INLINEASM)
43 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
45 const MCInstrDesc &Desc = MI->getDesc();
546 bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const {
548 return MI->isAsCheapAsAMove();
550 switch (MI->getOpcode()) {
559 return (MI->getOperand(3).getImm() == 0);
589 bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument
612 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
1043 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
1066 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
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H A DAArch64RegisterInfo.h75 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
76 bool isFrameOffsetLegal(const MachineInstr *MI,
81 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
/external/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h187 SUnit *newSUnit(MachineInstr *MI);
189 /// getSUnit - Return an existing SUnit for this MI, or NULL.
190 SUnit *getSUnit(MachineInstr *MI) const;
257 bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO);
261 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) { argument
265 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
272 /// getSUnit - Return an existing SUnit for this MI, or NULL.
273 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
274 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
H A DStackMaps.h26 /// \brief MI-level patchpoint operands.
28 /// MI patchpoint operations take the form:
45 const MachineInstr *MI; member in class:llvm::PatchPointOpers
49 explicit PatchPointOpers(const MachineInstr *MI);
60 return MI->getOperand(getMetaIdx(Pos));
69 + MI->getOperand(getMetaIdx(NArgPos)).getImm();
123 /// MI must be a raw STACKMAP, not a PATCHPOINT.
124 void recordStackMap(const MachineInstr &MI);
127 void recordPatchPoint(const MachineInstr &MI);
175 /// lowering the MI t
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H A DLexicalScopes.h67 /// openInsnRange - This scope covers instruction range starting from MI.
68 void openInsnRange(const MachineInstr *MI) { argument
70 FirstInsn = MI;
73 Parent->openInsnRange(MI);
78 void extendInsnRange(const MachineInstr *MI) { argument
79 assert(FirstInsn && "MI Range is not open!");
80 LastInsn = MI;
82 Parent->extendInsnRange(MI);
H A DTargetSchedule.h55 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
87 /// \brief Return the number of issue slots required for this MI.
88 unsigned getNumMicroOps(const MachineInstr *MI,
168 unsigned computeInstrLatency(const MachineInstr *MI,
/external/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp442 // If starting offset isn't zero, insert a MI to materialize a new base.
524 // Thumb1: we might need to set base writeback when building the MI.
573 MachineInstr &MI = *MemOps[i].MBBI; local
580 if (MI.definesRegister(DefReg))
583 MachineOperand *UseOp = MI.findRegisterUseOperand(DefReg);
779 static bool definesCPSR(MachineInstr *MI) { argument
780 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
781 const MachineOperand &MO = MI->getOperand(i);
793 static bool isMatchingDecrement(MachineInstr *MI, unsigned Base, argument
797 if (!MI)
828 isMatchingIncrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument
863 getLSMultipleTransferSize(MachineInstr *MI) argument
1263 isMemoryOp(const MachineInstr *MI) argument
1330 getMemoryOpOffset(const MachineInstr *MI) argument
1384 MachineInstr *MI = &*MBBI; local
1859 concatenateMemOperands(MachineInstr *MI, MachineInstr *Op0, MachineInstr *Op1) argument
2122 MachineInstr *MI = MBBI; local
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/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp311 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
316 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
321 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
326 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
331 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
336 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
341 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
398 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, argument
425 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
428 if (RegDecoder(MI, tm
444 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
483 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
522 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
565 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
609 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
658 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
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/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h168 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI, argument
171 return ComplexDeprecationInfo(MI, STI, Info);
286 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const { argument
292 if (hasDefOfPhysReg(MI, PC, RI))
298 for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
299 if (MI.getOperand(i).isReg() &&
300 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
563 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, argument
566 if (MI.getOperand(i).isReg() &&
567 RI.isSubRegisterEq(Reg, MI
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/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2576 // Split MBB after MI and return the new block (the one that contains
2577 // instructions after MI).
2578 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI, argument
2582 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2587 // Split MBB before MI and return the new block (the one that contains MI).
2588 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI, argument
2591 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2596 // Force base value Base into a register before MI. Return the register.
2597 static unsigned forceReg(MachineInstr *MI, MachineOperan argument
2614 emitSelect(MachineInstr *MI, MachineBasicBlock *MBB) const argument
2661 emitCondStore(MachineInstr *MI, MachineBasicBlock *MBB, unsigned StoreOpcode, unsigned STOCOpcode, bool Invert) const argument
2728 emitAtomicLoadBinary(MachineInstr *MI, MachineBasicBlock *MBB, unsigned BinOpcode, unsigned BitSize, bool Invert) const argument
2852 emitAtomicLoadMinMax(MachineInstr *MI, MachineBasicBlock *MBB, unsigned CompareOpcode, unsigned KeepOldMask, unsigned BitSize) const argument
2967 emitAtomicCmpSwapW(MachineInstr *MI, MachineBasicBlock *MBB) const argument
3083 emitExt128(MachineInstr *MI, MachineBasicBlock *MBB, bool ClearEven, unsigned SubReg) const argument
3115 emitMemMemWrapper(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode) const argument
3285 emitStringWrapper(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode) const argument
3345 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const argument
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/external/clang/lib/Lex/
H A DPPDirectives.cpp53 return &(MIChain->MI);
57 MacroInfo *MI = AllocateMacroInfo(); local
58 new (MI) MacroInfo(L);
59 return MI;
71 MacroInfo *MI = &MIChain->MI; local
72 new (MI) MacroInfo(L);
73 MI->FromASTFile = true;
74 MI->setOwningModuleID(SubModuleID);
75 return MI;
79 AllocateDefMacroDirective(MacroInfo *MI, SourceLocation Loc, bool isImported) argument
103 ReleaseMacroInfo(MacroInfo *MI) argument
1790 ReadMacroDefinitionArgList(MacroInfo *MI, Token &Tok) argument
1901 MacroInfo *MI = AllocateMacroInfo(MacroNameTok.getLocation()); local
2152 const MacroInfo *MI = MD ? MD->getMacroInfo() : nullptr; local
2205 MacroInfo *MI = MD ? MD->getMacroInfo() : nullptr; local
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/external/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp97 const MachineInstr *MI) {
124 lowerOperand(MI->getOperand(0), MCOp);
130 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument
134 if (MI->isDebugValue()) {
138 PrintDebugValueComment(MI, OS);
143 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
147 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
153 // The required alignment is specified on the basic block holding this MI.
155 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
156 unsigned CPIdx = (unsigned)MI
96 emitPseudoIndirectBranch(MCStreamer &OutStreamer, const MachineInstr *MI) argument
438 PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant,const char *ExtraCode, raw_ostream &O) argument
539 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
559 printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) argument
623 printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O) argument
632 printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O) argument
642 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) argument
653 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) argument
663 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier) argument
985 PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS) argument
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/external/clang/include/clang/Lex/
H A DTokenLexer.h109 TokenLexer(Token &Tok, SourceLocation ILEnd, MacroInfo *MI, argument
112 Init(Tok, ILEnd, MI, ActualArgs);
119 void Init(Token &Tok, SourceLocation ILEnd, MacroInfo *MI,
/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp102 MachineInstr* MI = *i; local
103 assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
106 MachineOperand& MO = MI->getOperand(2);
224 MachineBasicBlock::iterator MI,
259 TII.storeRegToStackSlot(MBB, MI, SuperReg, true,
267 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC,
278 MachineBasicBlock::iterator MI,
313 TII.loadRegFromStackSlot(MBB, MI, SuperReg, CSI[i+1].getFrameIdx(),
321 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
331 MachineInstr &MI local
222 spillCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
276 restoreCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
[all...]

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