/external/pdfium/core/src/fxcodec/lcms2/lcms2-2.6/src/ |
H A D | cmsopt.c | 552 cmsPipeline* Dest = NULL; local 586 Dest = cmsPipelineAlloc(Src ->ContextID, Src ->InputChannels, Src ->OutputChannels); 587 if (!Dest) return FALSE; 603 if(!cmsPipelineInsertStage(Dest, cmsAT_BEGIN, NewPreLin)) 618 if (!cmsPipelineInsertStage(Dest, cmsAT_END, CLUT)) { 636 if (!cmsPipelineInsertStage(Dest, cmsAT_END, NewPostLin)) 660 cmsPipelineFree(Dest); 681 _cmsPipelineSetOptimizationParameters(Dest, (_cmsOPTeval16Fn) DataCLUT->Params->Interpolation.Lerp16, DataCLUT->Params, NULL, NULL); 685 p16 = PrelinOpt16alloc(Dest ->ContextID, 687 Dest 1273 cmsPipeline* Dest = NULL; local 1489 SetMatShaper(cmsPipeline* Dest, cmsToneCurve* Curve1[3], cmsMAT3* Mat, cmsVEC3* Off, cmsToneCurve* Curve2[3], cmsUInt32Number* OutputFormat) argument 1547 cmsPipeline* Dest, *Src; local [all...] |
/external/clang/include/clang/Analysis/Analyses/ |
H A D | ThreadSafetyTIL.h | 1129 Store(SExpr *P, SExpr *V) : SExpr(COP_Store), Dest(P), Source(V) {} 1130 Store(const Store &S, SExpr *P, SExpr *V) : SExpr(S), Dest(P), Source(V) {} 1132 SExpr *destination() { return Dest.get(); } // Address to store to 1133 const SExpr *destination() const { return Dest.get(); } 1140 auto Np = Vs.traverse(Dest, Vs.subExprCtx(Ctx)); 1153 SExprRef Dest; member in class:clang::threadSafety::Store
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/external/clang/lib/CodeGen/ |
H A D | CGClass.cpp | 442 llvm::Value *Dest = LHS.getAddress(); local 444 Dest = CGF.Builder.CreateInBoundsGEP(Dest, ArrayIndex, "destaddress"); 450 LV.setAddress(Dest); 835 LValue Dest = CGF.EmitLValueForFieldInitialization(DestLV, FirstField); local 840 emitMemcpyIR(Dest.isBitField() ? Dest.getBitFieldAddr() : Dest.getAddress(),
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H A D | CGBuiltin.cpp | 623 std::pair<llvm::Value*, unsigned> Dest = local 626 Builder.CreateMemSet(Dest.first, Builder.getInt8(0), SizeVal, 627 Dest.second, false); 628 return RValue::get(Dest.first); 632 std::pair<llvm::Value*, unsigned> Dest = local 637 unsigned Align = std::min(Dest.second, Src.second); 638 Builder.CreateMemCpy(Dest.first, Src.first, SizeVal, Align, false); 639 return RValue::get(Dest.first); 650 std::pair<llvm::Value*, unsigned> Dest = local 655 unsigned Align = std::min(Dest 677 std::pair<llvm::Value*, unsigned> Dest = local 689 std::pair<llvm::Value*, unsigned> Dest = local 700 std::pair<llvm::Value*, unsigned> Dest = local 716 std::pair<llvm::Value*, unsigned> Dest = local [all...] |
/external/clang/utils/TableGen/ |
H A D | NeonEmitter.cpp | 451 void emitReverseVariable(Variable &Dest, Variable &Src); 1175 void Intrinsic::emitReverseVariable(Variable &Dest, Variable &Src) { argument 1176 if (Dest.getType().getNumVectors() > 1) { 1179 for (unsigned K = 0; K < Dest.getType().getNumVectors(); ++K) { 1180 OS << " " << Dest.getName() << ".val[" << utostr(K) << "] = " 1184 for (int J = Dest.getType().getNumElements() - 1; J >= 0; --J) 1190 OS << " " << Dest.getName() 1192 for (int J = Dest.getType().getNumElements() - 1; J >= 0; --J)
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/external/llvm/include/llvm/IR/ |
H A D | IRBuilder.h | 543 BranchInst *CreateBr(BasicBlock *Dest) { argument 544 return Insert(BranchInst::Create(Dest)); 558 SwitchInst *CreateSwitch(Value *V, BasicBlock *Dest, unsigned NumCases = 10, argument 560 return Insert(addBranchWeights(SwitchInst::Create(V, Dest, NumCases),
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/external/llvm/lib/IR/ |
H A D | Instructions.cpp | 3394 void SwitchInst::addCase(ConstantInt *OnVal, BasicBlock *Dest) { argument 3404 Case.setSuccessor(Dest);
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H A D | Core.cpp | 405 void LLVMGetParamTypes(LLVMTypeRef FunctionTy, LLVMTypeRef *Dest) { argument 409 *Dest++ = wrap(*I); 449 void LLVMGetStructElementTypes(LLVMTypeRef StructTy, LLVMTypeRef *Dest) { argument 453 *Dest++ = wrap(*I); 685 void LLVMGetMDNodeOperands(LLVMValueRef V, LLVMValueRef *Dest) argument 690 Dest[i] = wrap(N->getOperand(i)); 701 void LLVMGetNamedMetadataOperands(LLVMModuleRef M, const char* name, LLVMValueRef *Dest) argument 707 Dest[i] = wrap(N->getOperand(i)); 2037 LLVMValueRef LLVMBuildBr(LLVMBuilderRef B, LLVMBasicBlockRef Dest) { argument 2038 return wrap(unwrap(B)->CreateBr(unwrap(Dest))); 2081 LLVMAddCase(LLVMValueRef Switch, LLVMValueRef OnVal, LLVMBasicBlockRef Dest) argument 2086 LLVMAddDestination(LLVMValueRef IndirectBr, LLVMBasicBlockRef Dest) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 181 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len, 2428 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, argument 2458 RV = ARMEmitStore(VT, ResultReg, Dest); 2464 Dest.Offset += Size; 2526 Address Dest, Src; local 2527 if (!ARMComputeAddress(MTI.getRawDest(), Dest) || 2531 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
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H A D | ARMISelLowering.cpp | 3582 SDValue Dest = Op.getOperand(4); local 3608 Chain, Dest, ARMcc, CCR, Cmp); 3620 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 3632 SDValue Dest = Op.getOperand(4); local 3640 Chain, Dest, ARMcc, CCR, Cmp); 3660 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 3664 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 2290 SDValue Dest = Op.getOperand(4); local 2316 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1943 unsigned Dest = MI->getOperand(0).getReg(); local 2029 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 2039 LV->replaceKillInstruction(Dest, MI, ExtMI); 2069 const MachineOperand &Dest = MI->getOperand(0); local 2090 .addOperand(Dest).addOperand(Src).addImm(M); 2106 .addOperand(Dest).addOperand(Src).addImm(M); 2121 .addOperand(Dest) 2141 .addOperand(Dest) 2159 .addOperand(Dest) 2181 .addOperand(Dest) [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenDAGPatterns.cpp | 2481 TreePatternNode *Dest = Pat->getChild(i); local 2482 if (!Dest->isLeaf()) 2485 DefInit *Val = dyn_cast<DefInit>(Dest->getLeafValue()); 2522 TreePatternNode *Dest = Pat->getChild(i); local 2523 if (!Dest->isLeaf()) 2526 DefInit *Val = dyn_cast<DefInit>(Dest->getLeafValue()); 2534 if (Dest->getName().empty()) 2536 if (InstResults.count(Dest->getName())) 2537 I->error("cannot set '" + Dest->getName() +"' multiple times"); 2538 InstResults[Dest [all...] |
/external/clang/lib/Sema/ |
H A D | SemaInit.cpp | 4434 const ArrayType *Dest, 4438 if (Context.hasSameType(QualType(Dest, 0), QualType(Source, 0))) 4442 if (!Context.hasSameType(Dest->getElementType(), Source->getElementType())) 4447 return Source->isConstantArrayType() && Dest->isIncompleteArrayType(); 4433 hasCompatibleArrayTypes(ASTContext &Context, const ArrayType *Dest, const ArrayType *Source) argument
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H A D | SemaChecking.cpp | 4082 const Expr *Dest = Call->getArg(ArgIdx)->IgnoreParenImpCasts(); local 4085 QualType DestTy = Dest->getType(); 4106 Dest->Profile(DestID, Context, true); 4113 if (const UnaryOperator *UnaryOp = dyn_cast<UnaryOperator>(Dest)) 4124 SourceRange DSR = Dest->getSourceRange(); 4159 DiagRuntimeBehavior(LenExpr->getExprLoc(), Dest, 4162 << PointeeTy << Dest->getSourceRange() 4186 Dest->getExprLoc(), Dest, 4194 Dest [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1084 unsigned Dest = MI->getOperand(0).getReg(); local 1216 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1249 unsigned Dest = MI->getOperand(0).getReg(); local 1285 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1287 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1316 unsigned Dest = MI->getOperand(0).getReg(); local 1438 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1509 SDValue Dest = Op.getOperand(2); local 1526 FCC0, Dest, CondRes);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 1701 SDValue Dest = Op.getOperand(4); local 1708 DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue); 2741 unsigned Dest = MI->getOperand(0).getReg(); local 2786 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ] 2790 // %Dest = CS %OldVal, %NewVal, Disp(%Base) 2796 .addReg(Dest).addMBB(LoopMBB); 2834 BuildMI(MBB, DL, TII->get(CSOpcode), Dest) 2864 unsigned Dest = MI->getOperand(0).getReg(); local 2911 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ] 2918 .addReg(Dest) 2975 unsigned Dest = MI->getOperand(0).getReg(); local 3092 unsigned Dest = MI->getOperand(0).getReg(); local [all...] |
/external/llvm/lib/Transforms/Utils/ |
H A D | SimplifyCFG.cpp | 80 BasicBlock *Dest; member in struct:__anon26360::ValueEqualityComparisonCase 82 ValueEqualityComparisonCase(ConstantInt *Value, BasicBlock *Dest) argument 83 : Value(Value), Dest(Dest) {} 90 bool operator==(BasicBlock *RHSDest) const { return Dest == RHSDest; } 611 ThisCases[0].Dest->removePredecessor(TI->getParent()); 665 if (PredCases[i].Dest == TIBB) { 677 TheRealDest = ThisCases[i].Dest; 829 if (PredCases[i].Dest != BB) 857 BBCases[i].Dest ! 3964 BasicBlock *Dest = IBI->getDestination(i); local [all...] |
/external/llvm/bindings/ocaml/llvm/ |
H A D | llvm_ocaml.c | 1580 LLVMBasicBlockRef Dest) { 1581 LLVMAddCase(Switch, OnVal, Dest); 1594 LLVMBasicBlockRef Dest) { 1595 LLVMAddDestination(IndirectBr, Dest); 1579 llvm_add_case(LLVMValueRef Switch, LLVMValueRef OnVal, LLVMBasicBlockRef Dest) argument 1593 llvm_add_destination(LLVMValueRef IndirectBr, LLVMBasicBlockRef Dest) argument
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 3594 "Dest and insert subvector source types must match!"); 6337 bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, argument 6339 if (*this == Dest) return true; 6349 if (!getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 6357 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 774 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB] 2837 SDValue Dest = Op.getOperand(4); local 2876 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest, 2904 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest); 2907 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest); 2924 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest); 2927 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest); 2933 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, 2946 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp); 2949 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Va 7587 SDValue Dest = N->getOperand(1); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 3348 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 3350 Callee = SDValue(Dest, 0); 7081 unsigned Dest = MI->getOperand(0).getReg(); local 7097 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); 7112 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ? local 7117 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
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