/external/llvm/lib/CodeGen/ |
H A D | RegisterScavenging.cpp | 128 const MachineOperand &MO = MI->getOperand(i); local 129 if (MO.isRegMask()) 130 (isPred ? DefRegs : KillRegs).setBitsNotInMask(MO.getRegMask()); 131 if (!MO.isReg()) 133 unsigned Reg = MO.getReg(); 137 if (MO.isUse()) { 139 if (MO.isUndef()) 141 if (!isPred && MO.isKill()) 144 assert(MO.isDef()); 145 if (!isPred && MO 202 const MachineOperand &MO = MI->getOperand(i); local 309 const MachineOperand &MO = MI->getOperand(i); local 371 MachineOperand &MO = I->getOperand(i); local [all...] |
H A D | StackSlotColoring.cpp | 150 MachineOperand &MO = MI->getOperand(i); local 151 if (!MO.isFI()) 153 int FI = MO.getIndex(); 346 MachineOperand &MO = MI->getOperand(i); local 347 if (!MO.isFI()) 349 int OldFI = MO.getIndex(); 355 MO.setIndex(NewFI);
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H A D | TargetSchedule.cpp | 131 const MachineOperand &MO = MI->getOperand(i); local 132 if (MO.isReg() && MO.isDef()) 147 const MachineOperand &MO = MI->getOperand(i); local 148 if (MO.isReg() && MO.readsReg())
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H A D | VirtRegMap.cpp | 304 MachineOperand &MO = *MOI; local 305 if (!MO.isGlobal()) 307 const Function *Func = dyn_cast<Function>(MO.getGlobal()); 321 MachineOperand &MO = *MOI; local 324 if (MO.isRegMask()) 325 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask()); 330 if (MO.isReg() && MO.getReg()) 332 TargetRegisterInfo::isVirtualRegister(MO.getReg()) ? 333 VRM->getPhys(MO [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 64 MachineOperand &MO = MI->getOperand(i); local 65 if (!MO.isReg()) 67 unsigned Reg = MO.getReg(); 70 if (MO.isUse())
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 106 MachineOperand& MO = MI->getOperand(2); local 107 assert(MO.isImm() && "Expected immediate"); 108 MO.setImm(MFI->getMaxCallFrameSize());
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/external/llvm/lib/Target/Mips/ |
H A D | MipsCodeEmitter.cpp | 103 const MachineOperand &MO) const; 106 const MachineOperand &MO) const; 173 const MachineOperand &MO) const { 189 MachineOperand MO = MI.getOperand(OpNo); local 190 if (MO.isGlobal()) 191 emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true); 192 else if (MO.isSymbol()) 193 emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO)); 233 MachineOperand MO = MI.getOperand(OpNo); local [all...] |
H A D | MipsLongBranch.cpp | 106 const MachineOperand &MO = Br.getOperand(I); local 108 if (MO.isMBB()) 109 return MO.getMBB(); 227 MachineOperand &MO = Br->getOperand(I); local 229 if (!MO.isReg()) { 230 assert(MO.isMBB() && "MBB operand expected."); 234 MIB.addReg(MO.getReg());
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H A D | MipsOptimizePICCall.cpp | 108 MachineOperand &MO = MI.getOperand(0); 110 if (!MO.isReg() || !MO.isUse() || 111 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) 114 return &MO; 151 MachineOperand &MO = MI.getOperand(I); local 152 if (MO.isReg() && MO.getReg() == Reg) { 251 MachineOperand *MO = getCallTargetRegOpnd(MI); 254 if (!MO) [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCTRLoops.cpp | 557 const MachineOperand &MO = MI->getOperand(i); local 558 if (MO.isReg()) { 559 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8)) 561 } else if (MO.isRegMask()) { 562 if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8))
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUAsmPrinter.cpp | 166 MachineOperand & MO = MI.getOperand(op_idx); local 167 if (!MO.isReg()) 169 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff; 233 MachineOperand &MO = MI.getOperand(op_idx); local 237 if (!MO.isReg()) { 240 unsigned reg = MO.getReg();
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H A D | R600MachineScheduler.cpp | 163 MachineOperand &MO = *It; local 164 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X) 367 MachineOperand &MO = *It; local 368 if (MO.isReg() && !MO.isDef() && 369 MO.getReg() == DestReg)
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H A D | R600OptimizeVectorRegisters.cpp | 69 MachineOperand &MO = Instr->getOperand(i); local 71 if (isImplicitlyDef(MRI, MO.getReg())) 74 RegToChan[MO.getReg()] = Chan;
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 49 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 171 const MCOperand &MO, 174 if (MO.isReg()) { 176 return MRI.getEncodingValue(MO.getReg()); 177 return getHWReg(MO.getReg()); 180 assert(MO.isImm()); 181 return MO.getImm(); 170 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixup, const MCSubtargetInfo &STI) const argument
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/external/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 254 const MachineOperand &MO = candidate->getOperand(i); local 255 if (!MO.isReg()) 258 unsigned Reg = MO.getReg(); 260 if (MO.isDef()) { 265 if (MO.isUse()) { 309 const MachineOperand &MO = MI->getOperand(i); local 310 if (!MO.isReg()) 313 unsigned Reg = MO.getReg(); 316 if (MO.isDef()) 318 if (MO 353 const MachineOperand &MO = I->getOperand(structSizeOpNum); local [all...] |
H A D | SparcCodeEmitter.cpp | 74 const MachineOperand &MO) const; 88 const MachineOperand &MO) const; 178 const MachineOperand &MO) const { 179 if (MO.isReg()) 180 return TM.getRegisterInfo()->getEncodingValue(MO.getReg()); 181 else if (MO.isImm()) 182 return static_cast<unsigned>(MO.getImm()); 183 else if (MO.isGlobal()) 184 emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO)); 197 const MachineOperand MO = MI.getOperand(opIdx); local 203 const MachineOperand MO = MI.getOperand(opIdx); local 209 const MachineOperand MO = MI.getOperand(opIdx); local 215 const MachineOperand MO = MI.getOperand(opIdx); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 181 const MachineOperand& MO = MI.getOperand(i); local 182 if (MO.isReg()) { 183 unsigned Reg = MO.getReg(); 195 const MachineOperand& MO = MI.getOperand(i); local 196 if (X86InstrInfo::isX86_64ExtendedReg(MO)) 207 const MachineOperand& MO = MI.getOperand(i); local 208 if (MO.isReg()) { 209 if (X86InstrInfo::isX86_64ExtendedReg(MO)) 228 const MachineOperand& MO = MI.getOperand(i); local 229 if (MO 242 const MachineOperand& MO = MI.getOperand(i); local [all...] |
H A D | X86InstrBuilder.h | 61 void getFullAddress(SmallVectorImpl<MachineOperand> &MO) { argument 65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, 69 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex)); 72 MO.push_back(MachineOperand::CreateImm(Scale)); 73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, 77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); 79 MO.push_back(MachineOperand::CreateImm(Disp)); 81 MO.push_back(MachineOperand::CreateReg(0, false, false,
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H A D | X86InstrInfo.h | 116 inline static bool isScale(const MachineOperand &MO) { argument 117 return MO.isImm() && 118 (MO.getImm() == 1 || MO.getImm() == 2 || 119 MO.getImm() == 4 || MO.getImm() == 8); 379 static bool isX86_64ExtendedReg(const MachineOperand &MO) { argument 380 if (!MO.isReg()) return false; 381 return X86II::isX86_64ExtendedReg(MO.getReg());
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H A D | X86VZeroUpper.cpp | 117 static bool clobbersAllYmmRegs(const MachineOperand &MO) { argument 119 if (!MO.clobbersPhysReg(reg)) 127 const MachineOperand &MO = MI->getOperand(i); local 128 if (MI->isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO)) 130 if (!MO.isReg()) 132 if (MO.isDebug()) 134 if (isYmmReg(MO.getReg())) 145 const MachineOperand &MO = MI->getOperand(i); local 146 if (!MO [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreAsmPrinter.cpp | 214 const MachineOperand &MO = MI->getOperand(opNum); local 215 switch (MO.getType()) { 217 O << XCoreInstPrinter::getRegisterName(MO.getReg()); 220 O << MO.getImm(); 223 O << *MO.getMBB()->getSymbol(); 226 O << *getSymbol(MO.getGlobal()); 230 << '_' << MO.getIndex(); 233 O << *GetBlockAddressSymbol(MO.getBlockAddress());
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 245 MachineOperand &MO = MI.getOperand(i); local 247 if (MO.isReg() && MO.isDef()) { 248 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 254 MRI.setRegClass(MO.getReg(), newRegClass);
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 141 const MCOperand &MO, 143 if (MO.isReg()) { 144 return getRegBinaryCode(MO.getReg()); 145 } else if (MO.isImm()) { 146 return MO.getImm(); 147 } else if (MO.isFPImm()) { 234 const MCOperand &MO = MI.getOperand(opIdx); local 235 if (MO.isReg()) { 241 } else if (MO 140 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 406 MachineOperand &MO = Cond[1]; local 407 switch (MO.getImm()) { 409 MO.setImm(OPCODE_IS_NOT_ZERO_INT); 412 MO.setImm(OPCODE_IS_ZERO_INT); 415 MO.setImm(OPCODE_IS_NOT_ZERO); 418 MO.setImm(OPCODE_IS_ZERO);
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/external/llvm/include/llvm/MC/ |
H A D | MCInst.h | 192 inline raw_ostream& operator<<(raw_ostream &OS, const MCOperand &MO) { argument 193 MO.print(OS, nullptr);
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