/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 85 const MachineRegisterInfo *MRI; member in struct:__anon26019::HexagonPeephole 118 MRI = &MF.getRegInfo(); 250 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsAsmBackend.cpp | 396 const MCRegisterInfo &MRI, 404 const MCRegisterInfo &MRI, 412 const MCRegisterInfo &MRI, 420 const MCRegisterInfo &MRI, 395 createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument 403 createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument 411 createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument 419 createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.cpp | 48 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local 69 unsigned DReg = MRI->getDwarfRegNum(Reg, true);
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/external/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.cpp | 33 const MCRegisterInfo &MRI, 35 : MCInstPrinter(MAI, MII, MRI) { 32 NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 38 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); 40 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 154 const MCRegisterInfo &MRI, 153 createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.cpp | 69 const MCRegisterInfo &MRI, 71 return new AMDGPUInstPrinter(MAI, MII, MRI); 75 const MCRegisterInfo &MRI, 79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); 81 return createR600MCCodeEmitter(MCII, MRI, STI); 65 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 74 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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H A D | SIMCCodeEmitter.cpp | 41 const MCRegisterInfo &MRI; member in class:__anon26111::SIMCCodeEmitter 52 : MCII(mcii), MRI(mri) { } 70 const MCRegisterInfo &MRI, 73 return new SIMCCodeEmitter(MCII, MRI, Ctx); 177 return MRI.getEncodingValue(MO.getReg()); 69 createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.h | 32 MachineRegisterInfo *MRI; member in class:llvm::R600SchedStrategy 71 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
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H A D | SIFixSGPRCopies.cpp | 88 const MachineRegisterInfo &MRI, 92 const MachineRegisterInfo &MRI, 96 const MachineRegisterInfo &MRI) const; 118 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local 124 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 135 const MachineRegisterInfo &MRI, 143 const TargetRegisterClass *RC = MRI.getRegClass(Reg); 146 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) { 149 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, 133 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument 159 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument 197 MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 76 const MCRegisterInfo &MRI, 75 createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcFrameLowering.cpp | 112 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local 113 unsigned regFP = MRI->getDwarfRegNum(SP::I6, true); 126 unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true); 127 unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true); 191 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) argument 195 if (MRI->isPhysRegUsed(reg)) 199 if (MRI->isPhysRegUsed(reg)) 208 MachineRegisterInfo &MRI = MF.getRegInfo(); local 212 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed 213 || MRI 219 MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 96 const MCRegisterInfo &MRI, 95 createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &MCSTI, MCContext &Ctx) argument
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H A D | SystemZMCTargetDesc.cpp | 97 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, 102 MRI.getDwarfRegNum(SystemZ::R15D, true), 179 const MCRegisterInfo &MRI, 181 return new SystemZInstPrinter(MAI, MII, MRI); 175 createSystemZMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86ATTInstPrinter.h | 26 const MCRegisterInfo &MRI) 27 : MCInstPrinter(MAI, MII, MRI) {} 25 X86ATTInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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H A D | X86IntelInstPrinter.h | 27 const MCRegisterInfo &MRI) 28 : MCInstPrinter(MAI, MII, MRI) {} 26 X86IntelInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.cpp | 68 const MCRegisterInfo &MRI, 70 return new AMDGPUInstPrinter(MAI, MII, MRI); 64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 317 MachineRegisterInfo &MRI = MF.getRegInfo(); local 319 if (!MRI.isLiveIn(Reg)) { 320 VirtualRegister = MRI.createVirtualRegister(RC); 321 MRI.addLiveIn(Reg, VirtualRegister); 323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
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H A D | AMDGPUInstrInfo.cpp | 241 MachineRegisterInfo &MRI = MF.getRegInfo(); local 249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 254 MRI.setRegClass(MO.getReg(), newRegClass);
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H A D | R600ISelLowering.cpp | 57 MachineRegisterInfo &MRI = MF->getRegInfo(); local 111 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister); 120 unsigned NewAddr = MRI.createVirtualRegister( 122 unsigned ShiftValue = MRI.createVirtualRegister( 157 unsigned t0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 158 unsigned t1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 179 unsigned t0 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass); 180 unsigned t1 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass); 260 MachineRegisterInfo &MRI = MF.getRegInfo(); local 263 if (!MRI [all...] |
H A D | SIISelLowering.cpp | 69 MachineRegisterInfo & MRI = BB->getParent()->getRegInfo(); local 127 LowerSI_INTERP(MI, *BB, I, MRI); 130 LowerSI_INTERP_CONST(MI, *BB, I, MRI); 133 LowerSI_KIL(MI, *BB, I, MRI); 136 LowerSI_V_CNDLT(MI, *BB, I, MRI); 150 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const 152 unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); 153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); 183 MachineRegisterInfo &MRI) const 189 unsigned M0 = MRI [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | LiveIntervalAnalysis.h | 52 MachineRegisterInfo* MRI; member in class:llvm::LiveIntervals
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H A D | LiveRangeEdit.h | 62 MachineRegisterInfo &MRI; member in class:llvm::LiveRangeEdit 121 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm), 125 ScannedRemattable(false) { MRI.setDelegate(this); } 127 ~LiveRangeEdit() { MRI.resetDelegate(this); }
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/external/llvm/lib/CodeGen/ |
H A D | SplitKit.h | 215 MachineRegisterInfo &MRI; member in class:llvm::SplitEditor
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H A D | TargetRegisterInfo.cpp | 269 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 270 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 285 if (MRI.isReserved(Phys))
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