Searched defs:Op (Results 51 - 75 of 272) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp566 Value *Op = CI->getArgOperand(0); local
567 Op = CallInst::Create(Int, Op, CI->getName(), CI);
569 CI->replaceAllUsesWith(Op);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp91 SDValue Op(Node, ResNo);
93 VRBaseMap.erase(Op);
94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
124 SDValue Op = User->getOperand(i); local
125 if (Op.getNode() != Node || Op.getResNo() != ResNo)
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
180 SDValue Op(Node, ResNo);
182 VRBaseMap.erase(Op);
183 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBas
279 getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap) argument
307 AddRegisterOperand(MachineInstrBuilder &MIB, SDValue Op, unsigned IIOpNum, const MCInstrDesc *II, DenseMap<SDValue, unsigned> &VRBaseMap, bool IsDebug, bool IsClone, bool IsCloned) argument
[all...]
H A DLegalizeTypes.h151 SDValue BitConvertToInteger(SDValue Op);
152 SDValue BitConvertVectorToIntegerVector(SDValue Op);
153 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
172 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
173 void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
180 /// GetPromotedInteger - Given a processed operand Op which was promoted to a
182 /// promoted value corresponding to the original type are exactly equal to Op.
186 /// For example, if Op is an i16 and was promoted to an i32, then this method
187 /// returns an i32, the lower 16 bits of which coincide with Op, and the upper
189 SDValue GetPromotedInteger(SDValue Op) { argument
199 SExtPromotedInteger(SDValue Op) argument
209 ZExtPromotedInteger(SDValue Op) argument
374 GetSoftenedFloat(SDValue Op) argument
502 GetScalarizedVector(SDValue Op) argument
608 GetWidenedVector(SDValue Op) argument
701 GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument
730 GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument
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H A DResourcePriorityQueue.cpp135 const SDValue &Op = ScegN->getOperand(i); local
136 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
344 const SDValue &Op = SU->getNode()->getOperand(i); local
345 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
346 if (isa<ConstantSDNode>(Op.getNode()))
498 const SDValue &Op = ScegN->getOperand(i); local
499 MVT VT = Op.getNode()->getSimpleValueType(Op
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H A DScheduleDAGSDNodes.cpp111 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, argument
115 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
H A DSelectionDAGPrinter.cpp93 SDValue Op = EI.getNode()->getOperand(EI.getOperand()); local
94 EVT VT = Op.getValueType();
/external/llvm/lib/TableGen/
H A DSetTheory.cpp68 // SetIntBinOp - Abstract base class for (Op S, N) operators.
76 PrintFatalError(Loc, "Operator requires (Op Set, Int) arguments: " +
260 void SetTheory::addOperator(StringRef Name, Operator *Op) { argument
261 Operators[Name] = Op;
292 Operator *Op = Operators.lookup(OpInit->getDef()->getName()); local
293 if (!Op)
295 Op->apply(*this, DagExpr, Elts, Loc);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h41 static inline const char *getAddrOpcStr(AddrOpc Op) { argument
42 return Op == sub ? "-" : "";
45 static inline const char *getShiftOpcStr(ShiftOpc Op) { argument
46 switch (Op) {
56 static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { argument
57 switch (Op) {
115 static inline unsigned getSORegOffset(unsigned Op) {
116 return Op >> 3;
118 static inline ShiftOpc getSORegShOp(unsigned Op) {
119 return (ShiftOpc)(Op
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/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp112 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
120 SDNode *SelectIndexedLoad(SDNode *Op);
121 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
288 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, argument
294 if (!SelectAddr(Op, Op0, Op1))
355 SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op, argument
360 IsLegalToFold(N1, Op, Op, OptLevel)) {
371 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
/external/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.cpp227 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, argument
230 OutOps.push_back(Op);
/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp138 const MCOperand &Op = MI->getOperand(OpNo); local
139 if (Op.isReg()) {
140 switch (Op.getReg()) {
146 printRegOperand(Op.getReg(), O);
149 } else if (Op.isImm()) {
150 printImmediate(Op.getImm(), O);
151 } else if (Op.isFPImm()) {
152 O << Op.getFPImm();
153 } else if (Op.isExpr()) {
154 const MCExpr *Exp = Op
198 const MCOperand &Op = MI->getOperand(OpNo); local
266 const MCOperand &Op = MI->getOperand(OpNo); local
383 unsigned Op = (SImm16 >> 4) & 0xF; local
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/external/llvm/lib/Target/R600/
H A DR600ExpandSpecialInstrs.cpp37 unsigned Op);
59 const MachineInstr *OldMI, unsigned Op) {
60 int OpIdx = TII->getOperandIdx(*OldMI, Op);
63 TII->setImmOperand(NewMI, Op, Val);
58 SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI, unsigned Op) argument
H A DR600Packetizer.cpp307 unsigned Op = TII->getOperandIdx(MI->getOpcode(), variable
309 MI->getOperand(Op).setImm(BS[i]);
311 unsigned Op = TII->getOperandIdx(MI->getOpcode(), variable
313 MI->getOperand(Op).setImm(BS.back());
H A DSIInsertWaits.cpp78 bool isOpRelevant(MachineOperand &Op);
81 RegInterval getRegInterval(MachineOperand &Op);
139 MachineOperand &Op = MI.getOperand(0); local
140 assert(Op.isReg() && "First LGKM operand must be a register!");
142 unsigned Reg = Op.getReg();
158 bool SIInsertWaits::isOpRelevant(MachineOperand &Op) { argument
161 if (!Op.isReg())
165 if (Op.isDef())
169 MachineInstr &MI = *Op.getParent();
181 return Op
187 getRegInterval(MachineOperand &Op) argument
226 MachineOperand &Op = MI.getOperand(i); local
327 MachineOperand &Op = MI.getOperand(i); local
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H A DSILowerControlFlow.cpp299 const MachineOperand &Op = MI.getOperand(0); local
308 if ((Op.isImm() || Op.isFPImm())) {
310 if (Op.isImm() ? (Op.getImm() & 0x80000000) :
311 Op.getFPImm()->isNegative()) {
318 .addOperand(Op);
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmInstrumentation.cpp58 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
61 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
64 void InstrumentMemOperand(MCParsedAsmOperand &Op, unsigned AccessSize,
79 MCParsedAsmOperand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
81 assert(Op.isMem() && "Op should be a memory operand.");
85 X86Operand &MemOp = static_cast<X86Operand &>(Op);
137 MCParsedAsmOperand &Op = *Operands[Ix]; local
138 if (Op.isMem())
139 InstrumentMemOperand(Op, AccessSiz
78 InstrumentMemOperand( MCParsedAsmOperand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out) argument
177 InstrumentMemOperandSmallImpl( X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out) argument
259 InstrumentMemOperandLargeImpl( X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out) argument
353 InstrumentMemOperandSmallImpl( X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out) argument
434 InstrumentMemOperandLargeImpl( X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out) argument
[all...]
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { argument
123 if (MI->getOperand(Op).isFI()) return true;
124 return Op+X86::AddrSegmentReg <= MI->getNumOperands() &&
125 MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
126 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) &&
127 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
128 (MI->getOperand(Op+X86::AddrDisp).isImm() ||
129 MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
130 MI->getOperand(Op+X86::AddrDisp).isCPI() ||
131 MI->getOperand(Op
134 isMem(const MachineInstr *MI, unsigned Op) argument
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/external/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp70 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
113 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, argument
119 switch (Op.getOpcode()) {
130 OutOps.push_back(Op.getOperand(0));
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombine.h153 Instruction *FoldOrWithConstants(BinaryOperator &I, Value *Op, Value *A,
232 Instruction *FoldOpIntoSelect(Instruction &Op, SelectInst *SI);
309 if (Instruction *Op = dyn_cast<Instruction>(*i))
310 Worklist.Add(Op);
327 unsigned ComputeNumSignBits(Value *Op, unsigned Depth = 0) const { argument
328 return llvm::ComputeNumSignBits(Op, DL, Depth);
380 Instruction *OptAndOp(Instruction *Op, ConstantInt *OpRHS,
/external/llvm/lib/Transforms/ObjCARC/
H A DObjCARC.h303 static inline bool IsPotentialRetainableObjPtr(const Value *Op) { argument
306 if (isa<Constant>(Op) || isa<AllocaInst>(Op))
309 if (const Argument *Arg = dyn_cast<Argument>(Op))
320 PointerType *Ty = dyn_cast<PointerType>(Op->getType());
328 static inline bool IsPotentialRetainableObjPtr(const Value *Op, argument
331 if (!IsPotentialRetainableObjPtr(Op))
335 if (AA.pointsToConstantMemory(Op))
339 if (const LoadInst *LI = dyn_cast<LoadInst>(Op))
/external/llvm/lib/Transforms/Utils/
H A DLoopUnroll.cpp50 Value *Op = I->getOperand(op); local
51 ValueToValueMapTy::iterator It = VMap.find(Op);
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp89 Operator *Op; // The Operation used to generate this value. member in struct:ShuffleVal
147 static const char *getZeroCostOpName(unsigned short Op) { argument
148 if (ShufTab[Op].Arg0 == 0x0123)
150 else if (ShufTab[Op].Arg0 == 0x4567)
162 std::cerr << " = " << ShufTab[ThisOp].Op->getName() << "(";
176 if (!ShufTab[Vals[ValNo]].Op->isOnlyLHSOperator()) {
222 ShufTab[0x0123].Op = nullptr;
225 ShufTab[0x4567].Op = nullptr;
304 Operator *Op = TheOperators[opnum];
307 unsigned ResultMask = Op
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/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) argument
82 switch (Op.getOpcode()) {
84 Op.getNode()->dump();
89 case ISD::SDIV: return LowerSDIV(Op, DAG);
90 case ISD::SREM: return LowerSREM(Op, DAG);
91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
93 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
95 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
96 case ISD::UDIVREM: return LowerUDIVREM(Op, DA
101 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument
149 LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const argument
163 LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const argument
180 LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const argument
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H A DR600ISelLowering.cpp245 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const argument
247 switch (Op.getOpcode()) {
248 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
249 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
250 case ISD::ROTL: return LowerROTL(Op, DAG);
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
254 SDValue Chain = Op.getOperand(0);
256 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
261 int64_t RegIndex = cast<ConstantSDNode>(Op
332 LowerBR_CC(SDValue Op, SelectionDAG &DAG) const argument
374 LowerROTL(SDValue Op, SelectionDAG &DAG) const argument
387 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const argument
499 LowerSETCC(SDValue Op, SelectionDAG &DAG) const argument
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H A DSIISelLowering.cpp261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const argument
263 switch (Op.getOpcode()) {
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
266 case ISD::LOAD: return LowerLOAD(Op, DAG);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
271 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
272 EVT VT = Op.getValueType();
277 default: return AMDGPUTargetLowering::LowerOperation(Op, DA
293 Loweri1ContextSwitch(SDValue Op, SelectionDAG &DAG, unsigned VCCNode) const argument
308 LowerBR_CC(SDValue Op, SelectionDAG &DAG) const argument
332 LowerLOAD(SDValue Op, SelectionDAG &DAG) const argument
374 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const argument
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