/external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
H A D | rc_test_helpers.c | 297 struct match_info Opcode; member in struct:inst_tokens 334 tokens.Opcode.String = inst_str + matches[1].rm_so; 335 tokens.Opcode.Length = match_length(matches, 1); 347 if (strncmp(tokens.Opcode.String, info->Name, tokens.Opcode.Length)) { 350 inst->U.I.Opcode = info->Opcode;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 95 bool R600InstrInfo::isMov(unsigned Opcode) const 99 switch(Opcode) { 111 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const 113 switch (Opcode) { 122 bool R600InstrInfo::isReductionOp(unsigned Opcode) const 124 switch(Opcode) { 132 bool R600InstrInfo::isCubeOp(unsigned Opcode) const 134 switch(Opcode) { 152 isPredicateSetter(unsigned Opcode) argument 154 switch (Opcode) { [all...] |
/external/llvm/include/llvm/IR/ |
H A D | Instruction.h | 100 static inline bool isBinaryOp(unsigned Opcode) { argument 101 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd; 104 /// @brief Determine if the Opcode is one of the shift instructions. 105 static inline bool isShift(unsigned Opcode) { argument 106 return Opcode >= Shl && Opcode <= AShr;
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H A D | Constants.h | 794 /// constant expressions. The Opcode field for the ConstantExpr class is 802 ConstantExpr(Type *ty, unsigned Opcode, Use *Ops, unsigned NumOps) argument 805 setValueSubclassData(Opcode); 915 static Constant *getBinOpIdentity(unsigned Opcode, Type *Ty); 921 static Constant *getBinOpAbsorber(unsigned Opcode, Type *Ty); 1003 static Constant *get(unsigned Opcode, Constant *C1, Constant *C2,
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/external/llvm/include/llvm/MC/ |
H A D | MCInst.h | 151 unsigned Opcode; member in class:llvm::MCInst 155 MCInst() : Opcode(0) {} 157 void setOpcode(unsigned Op) { Opcode = Op; } 158 unsigned getOpcode() const { return Opcode; }
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/external/llvm/lib/Analysis/ |
H A D | CostModel.cpp | 173 unsigned Opcode = BinOp->getOpcode(); local 220 else if (NextLevelBinOp->getOpcode() != Opcode) 242 unsigned &Opcode, Type *&Ty) { 284 Opcode = RdxStart->getOpcode(); 305 unsigned &Opcode, Type *&Ty) { 375 Opcode = RdxOpcode; 241 matchPairwiseReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, Type *&Ty) argument 304 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, Type *&Ty) argument
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H A D | TargetTransformInfo.cpp | 43 unsigned TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty, argument 45 return PrevTTI->getOperationCost(Opcode, Ty, OpTy); 174 unsigned TargetTransformInfo::getArithmeticInstrCost(unsigned Opcode, argument 178 return PrevTTI->getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 186 unsigned TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst, argument 188 return PrevTTI->getCastInstrCost(Opcode, Dst, Src); 191 unsigned TargetTransformInfo::getCFInstrCost(unsigned Opcode) const { 192 return PrevTTI->getCFInstrCost(Opcode); 195 unsigned TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, argument 197 return PrevTTI->getCmpSelInstrCost(Opcode, ValT 200 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const argument 205 getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace) const argument 228 getReductionCost(unsigned Opcode, Type *Ty, bool IsPairwise) const argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | BasicTargetTransformInfo.cpp | 104 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind, 108 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, 110 unsigned getCFInstrCost(unsigned Opcode) const override; 111 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 113 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, 115 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 121 unsigned getReductionCost(unsigned Opcode, Type *Ty, 289 unsigned BasicTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty, argument 294 int ISD = TLI->InstructionOpcodeToISD(Opcode); 323 unsigned Cost = TopTTI->getArithmeticInstrCost(Opcode, T 358 getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const argument 453 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const argument 491 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const argument 498 getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace) const argument 628 getReductionCost(unsigned Opcode, Type *Ty, bool IsPairwise) const argument [all...] |
H A D | MachineSSAUpdater.cpp | 114 MachineInstrBuilder InsertNewDef(unsigned Opcode, argument 120 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
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/external/llvm/lib/Target/ARM/ |
H A D | MLxExpansionPass.cpp | 191 unsigned Opcode = MCID.getOpcode(); local 192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) 199 static bool isFpMulInstruction(unsigned Opcode) { argument 200 switch (Opcode) {
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H A D | Thumb2SizeReduction.cpp | 891 unsigned Opcode = MI->getOpcode(); local 892 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 463 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg, argument 465 switch (Opcode) { 482 llvm_unreachable("unexpected Opcode in validImmediate");
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUInstrInfo.cpp | 328 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const { argument 330 default: return Opcode; 331 case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1); 332 case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2); 333 case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3); 342 int getMCOpcode(uint16_t Opcode, unsigned Gen) { argument 343 return getMCOpcode(Opcode);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZElimCompare.cpp | 168 unsigned Opcode = MI->getOpcode(); local 170 if (Opcode == SystemZ::AHI) 172 else if (Opcode == SystemZ::AGHI) 215 unsigned Opcode = TII->getLoadAndTest(MI->getOpcode()); local 216 if (!Opcode) 219 MI->setDesc(TII->get(Opcode)); 233 int Opcode = MI->getOpcode(); local 234 const MCInstrDesc &Desc = TII->get(Opcode);
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 86 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind, 90 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, 92 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 94 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, 96 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 102 unsigned getReductionCost(unsigned Opcode, Type *Ty, 109 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 181 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty, argument 187 int ISD = TLI->InstructionOpcodeToISD(Opcode); 403 return TargetTransformInfo::getArithmeticInstrCost(Opcode, T 522 getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const argument 682 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const argument 739 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const argument 778 getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace) const argument 837 getReductionCost(unsigned Opcode, Type *ValTy, bool IsPairwise) const argument 964 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const argument [all...] |
/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 291 unsigned Opcode = fieldFromInstruction(Insn, 11, 5); local 292 switch (Opcode) { 454 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | local 456 switch (Opcode) { 683 unsigned Opcode = fieldFromInstruction(Insn, 27, 5); local 684 switch (Opcode) {
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/external/llvm/lib/Transforms/Utils/ |
H A D | BypassSlowDivision.cpp | 232 unsigned Opcode = J->getOpcode(); local 233 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv; 234 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem; 235 bool UseSignedOp = Opcode == Instruction::SDiv || 236 Opcode == Instruction::SRem;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 95 bool R600InstrInfo::isMov(unsigned Opcode) const 99 switch(Opcode) { 111 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const 113 switch (Opcode) { 122 bool R600InstrInfo::isReductionOp(unsigned Opcode) const 124 switch(Opcode) { 132 bool R600InstrInfo::isCubeOp(unsigned Opcode) const 134 switch(Opcode) { 152 isPredicateSetter(unsigned Opcode) argument 154 switch (Opcode) { [all...] |
/external/chromium_org/sandbox/win/src/sidestep/ |
H A D | mini_disassembler_types.h | 117 // Everything that's in an Opcode (see below) except the three 140 struct Opcode { struct in namespace:sidestep 170 const Opcode* table_;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
H A D | radeon_opcodes.h | 243 rc_opcode Opcode; member in struct:rc_opcode_info 272 assert(rc_opcodes[opcode].Opcode == opcode);
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/external/chromium_org/third_party/tcmalloc/chromium/src/windows/ |
H A D | mini_disassembler_types.h | 156 // Everything that's in an Opcode (see below) except the three 179 struct Opcode { struct in namespace:sidestep 209 const Opcode* table_;
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/external/chromium_org/third_party/tcmalloc/vendor/src/windows/ |
H A D | mini_disassembler_types.h | 156 // Everything that's in an Opcode (see below) except the three 179 struct Opcode { struct in namespace:sidestep 209 const Opcode* table_;
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/external/chromium_org/tools/traceline/traceline/sidestep/ |
H A D | mini_disassembler_types.h | 117 // Everything that's in an Opcode (see below) except the three 140 struct Opcode { struct in namespace:sidestep 170 const Opcode* table_;
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/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | IvarInvalidationChecker.cpp | 677 BinaryOperatorKind Opcode = BO->getOpcode(); local 678 if (Opcode != BO_Assign && 679 Opcode != BO_EQ && 680 Opcode != BO_NE) 688 if (Opcode != BO_Assign && isZero(BO->getLHS())) {
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/external/llvm/lib/MC/MCAnalysis/ |
H A D | MCModuleYAML.cpp | 94 OpcodeEnum Opcode; member in struct:llvm::MCModuleYAML::Inst 193 IO.mapRequired("Inst", I.Opcode); 320 A.Insts[i].Opcode = MCDI.Inst.getOpcode(); 380 MI.setOpcode(II->Opcode);
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