Searched defs:RC (Results 51 - 75 of 138) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DPrologEpilogInserter.cpp286 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); local
303 unsigned Align = RC->getAlignment();
310 FrameIdx = MFI->CreateStackObject(RC->getSize(), Align, true);
316 MFI->CreateFixedSpillStackObject(RC->getSize(), FixedSlot->Offset);
355 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
357 RC, TRI);
383 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
384 TII.loadRegFromStackSlot(*MBB, I, Reg, CSI[i].getFrameIdx(), RC, TRI);
883 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg); local
884 unsigned ScratchReg = RS->scavengeRegister(RC,
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H A DExecutionDepsFix.cpp131 const TargetRegisterClass *const RC; member in class:__anon25744::ExeDepsFix
157 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
521 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
719 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
722 << RC->getName() << " **********\n");
727 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
737 // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC,
740 for (unsigned i = 0, e = RC
795 createExecutionDependencyFixPass(const TargetRegisterClass *RC) argument
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H A DPeepholeOptimizer.cpp377 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); local
391 unsigned NewVR = MRI->createVirtualRegister(RC);
H A DRegAllocFast.cpp168 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
202 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { argument
209 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
210 RC->getAlignment());
288 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg); local
289 int FI = getStackSpaceFor(LRI->VirtReg, RC);
291 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
516 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); local
520 !RC->contains(Hint) || !MRI->isAllocatable(Hint)))
536 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
626 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); local
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H A DTailDuplication.cpp404 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); local
409 unsigned NewDef = MRI->createVirtualRegister(RC);
441 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
442 unsigned NewReg = MRI->createVirtualRegister(RC);
H A DTargetInstrInfo.cpp284 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, argument
289 Size = RC->getSize();
306 assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
309 Offset = RC->getSize() - (Offset + Size);
361 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); local
364 return RC->contains(LiveOp.getReg()) ? RC : nullptr;
366 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
367 return RC;
421 const TargetRegisterClass *RC local
495 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); local
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H A DTargetLoweringBase.cpp916 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
917 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
982 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; local
983 if (!RC)
984 return std::make_pair(RC, 0);
988 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
992 const TargetRegisterClass *BestRC = RC;
/external/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp96 const TargetRegisterClass *RC, bool isVector,
248 // Prints the register in MO using class RC using the offset in the
252 const TargetRegisterClass *RC,
258 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
299 const TargetRegisterClass *RC; local
302 RC = &AArch64::FPR8RegClass;
305 RC = &AArch64::FPR16RegClass;
308 RC = &AArch64::FPR32RegClass;
311 RC = &AArch64::FPR64RegClass;
314 RC
251 printAsmRegInClass(const MachineOperand &MO, const TargetRegisterClass *RC, bool isVector, raw_ostream &O) argument
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H A DAArch64FrameLowering.cpp885 const TargetRegisterClass *RC = &AArch64::GPR64RegClass; local
886 int FI = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false);
H A DAArch64InstrInfo.cpp375 const TargetRegisterClass *RC = local
377 if (!RC)
385 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
386 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
399 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
400 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
495 const TargetRegisterClass *RC = nullptr; local
498 RC = &AArch64::GPR64RegClass;
502 RC = &AArch64::GPR32RegClass;
506 RC
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/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp99 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
105 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
115 unsigned DestReg, int FI, const TargetRegisterClass *RC,
122 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
97 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
114 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
H A DMipsFastISel.cpp86 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
91 unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, argument
325 const TargetRegisterClass *RC = &Mips::FGR32RegClass; local
326 unsigned DestReg = createResultReg(RC);
331 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; local
332 unsigned DestReg = createResultReg(RC);
346 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
347 unsigned DestReg = createResultReg(RC);
360 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
367 return Materialize32BitInt(Imm, RC);
370 Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
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H A DMipsSEFrameLowering.cpp134 const TargetRegisterClass *RC = RegInfo.intRegClass(4); local
135 unsigned VR = MRI.createVirtualRegister(RC);
138 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); local
155 unsigned VR = MRI.createVirtualRegister(RC);
160 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
177 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); local
178 unsigned VR0 = MRI.createVirtualRegister(RC);
179 unsigned VR1 = MRI.createVirtualRegister(RC);
186 TII.loadRegFromStack(MBB, I, VR0, FI, RC,
207 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); local
244 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); local
357 const TargetRegisterClass *RC = STI.isABI_N64() ? local
423 const TargetRegisterClass *RC = STI.isABI_N64() ? local
471 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
531 const TargetRegisterClass *RC = STI.hasMips64() ? local
545 const TargetRegisterClass *RC = STI.isABI_N64() ? local
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H A DMipsSEISelDAGToDAG.cpp135 const TargetRegisterClass *RC; local
138 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
140 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
142 V0 = RegInfo.createVirtualRegister(RC);
143 V1 = RegInfo.createVirtualRegister(RC);
860 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); local
863 CurDAG->getTargetConstant(RC->getID(),
H A DMipsSEInstrInfo.cpp185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
193 if (Mips::GPR32RegClass.hasSubClassEq(RC))
195 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
197 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
199 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
201 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
203 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
205 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
207 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
209 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
226 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
388 const TargetRegisterClass *RC = STI.isABI_N64() ? local
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/external/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.cpp110 const TargetRegisterClass *RC,
119 const TargetRegisterClass *RC,
264 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
106 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
116 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp83 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { argument
86 return *(RegInfo->getRegClass(RC).begin() + RegNo);
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp239 const CodeGenRegisterClass &RC = *RCs[i]; local
240 if (RC.contains(Reg)) {
241 ArrayRef<MVT::SimpleValueType> InVTs = RC.getValueTypes();
430 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, argument
432 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
/external/chromium_org/third_party/skia/third_party/lua/src/
H A Dlvm.c492 #define RC(i) check_exp(getCMode(GET_OPCODE(i)) == OpArgR, base+GETARG_C(i)) macro
/external/libogg/win32/
H A DMakefile98 RC = @RC@ macro
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp576 const TargetRegisterClass *RC = local
578 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
580 // If cross copy register class is the same as RC, then it must be
582 // If cross copy register class is not the same as RC, then it's
588 if (DestRC != RC) {
597 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
H A DSelectionDAGBuilder.cpp833 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); local
834 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
6162 const TargetRegisterClass *RC = PhysReg.second;
6164 ValueVT = *RC->vt_begin();
6169 RegVT = *RC->vt_begin();
6176 TargetRegisterClass::iterator I = RC->begin();
6178 assert(I != RC->end() && "Didn't find reg!");
6183 assert(I != RC->end() && "Ran out of registers to allocate!");
6194 if (const TargetRegisterClass *RC = PhysReg.second) {
6195 RegVT = *RC
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/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp145 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; local
146 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
154 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
156 const TargetRegisterClass *Super = RC;
157 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
171 return RC;
181 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
182 if (RC == &ARM::CCRRegClass)
184 return RC;
188 getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp148 const TargetRegisterClass* RC);
153 const TargetRegisterClass* RC);
342 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg); local
343 if (RC == &Hexagon::PredRegsRegClass) {
434 const TargetRegisterClass* RC) {
440 if (RC == &Hexagon::PredRegsRegClass)
753 const TargetRegisterClass* RC )
764 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
766 else if (RC != &Hexagon::PredRegsRegClass &&
1177 const TargetRegisterClass* RC local
432 PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument
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/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp391 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { argument
394 return *(RegInfo->getRegClass(RC).begin() + RegNo);

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