Searched defs:STI (Results 51 - 75 of 104) sorted by relevance

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/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmInstrumentation.cpp46 X86AddressSanitizer(const MCSubtargetInfo &STI) : STI(STI) {} argument
69 Out.EmitInstruction(Inst, STI);
75 const MCSubtargetInfo &STI; member in class:llvm::__anon26164::X86AddressSanitizer
147 X86AddressSanitizer32(const MCSubtargetInfo &STI) argument
148 : X86AddressSanitizer(STI) {}
313 X86AddressSanitizer64(const MCSubtargetInfo &STI) argument
314 : X86AddressSanitizer(STI) {}
494 const MCContext &Ctx, const MCSubtargetInfo &STI) {
493 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCContext &Ctx, const MCSubtargetInfo &STI) argument
[all...]
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp355 const MCSubtargetInfo &STI,
377 const MCSubtargetInfo &STI) {
351 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
372 createX86MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp56 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI) argument
58 (STI.is64Bit() ? X86::RIP : X86::EIP),
59 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
60 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
61 (STI.is64Bit() ? X86::RIP : X86::EIP)),
62 Subtarget(STI) {
H A DX86MCInstLower.cpp608 const MCSubtargetInfo& STI) {
618 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); local
665 OutStreamer.EmitInstruction(LEA, STI);
668 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); local
669 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); local
670 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI); local
682 .addExpr(tlsRef), STI); local
686 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) { argument
721 OS.EmitInstruction(MCInstBuilder(Opc), STI); local
724 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); local
605 LowerTlsAddr(MCStreamer &OutStreamer, X86MCInstLower &MCInstLowering, const MachineInstr &MI, const MCSubtargetInfo& STI) argument
731 .addReg(SegmentReg), STI); local
739 LowerSTACKMAP(MCStreamer &OS, StackMaps &SM, const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) argument
752 LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM, const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) argument
770 .addImm(CallTarget), STI); local
771 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI); local
[all...]
/external/llvm/lib/Target/XCore/MCTargetDesc/
H A DXCoreMCTargetDesc.cpp89 const MCSubtargetInfo &STI) {
84 createXCoreMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/tools/llvm-mc/
H A Dllvm-mc.cpp322 MCAsmInfo &MAI, MCSubtargetInfo &STI,
327 TheTarget->createMCAsmParser(STI, *Parser, MCII, MCOptions));
446 std::unique_ptr<MCSubtargetInfo> STI(
452 TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI);
461 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
472 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
475 FOS, CE, *STI, RelaxAll,
486 Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI,
499 Res = Disassembler::disassemble(*TheTarget, TripleName, *STI, *Str,
320 AssembleInput(const char *ProgName, const Target *TheTarget, SourceMgr &SrcMgr, MCContext &Ctx, MCStreamer &Str, MCAsmInfo &MAI, MCSubtargetInfo &STI, MCInstrInfo &MCII, MCTargetOptions &MCOptions) argument
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_debug.cpp217 const MCSubtargetInfo *STI = T->createMCSubtargetInfo(Triple, sys::getHostCPUName(), ""); local
218 OwningPtr<const MCDisassembler> DisAsm(T->createMCDisassembler(*STI));
251 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
254 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *STI));
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DSIMCCodeEmitter.cpp63 const MCSubtargetInfo &STI; member in class:__anon27323::SIMCCodeEmitter
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
125 createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/lib/MC/
H A DMCELFStreamer.cpp397 const MCSubtargetInfo &STI) {
398 this->MCObjectStreamer::EmitInstToFragment(Inst, STI);
406 const MCSubtargetInfo &STI) {
411 Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
396 EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &STI) argument
405 EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) argument
H A DMCObjectStreamer.cpp188 const MCSubtargetInfo &STI) {
189 MCStreamer::EmitInstruction(Inst, STI);
201 EmitInstToData(Inst, STI);
216 EmitInstToData(Relaxed, STI);
221 EmitInstToFragment(Inst, STI);
225 const MCSubtargetInfo &STI) {
228 MCRelaxableFragment *IF = new MCRelaxableFragment(Inst, STI);
234 STI);
187 EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) argument
224 EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp51 const MCSubtargetInfo &STI) const;
57 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
71 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI) const;
83 const MCSubtargetInfo &STI) const;
89 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) const;
102 const MCSubtargetInfo &STI) const;
108 const MCSubtargetInfo &STI) cons
206 createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
[all...]
/external/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp384 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>(); local
385 isLikeA9 = STI->isLikeA9() || STI->isSwift();
386 isSwift = STI->isSwift();
H A DThumb2SizeReduction.cpp138 const ARMSubtarget *STI; member in class:__anon26006::Thumb2SizeReduce
250 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
636 STI->avoidMOVsShifterOperand())
753 STI->avoidMOVsShifterOperand())
1007 STI = &TM.getSubtarget<ARMSubtarget>();
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp248 const MCSubtargetInfo &STI)
249 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
251 uint64_t Features = STI.getFeatureBits();
252 Triple T(STI.getTargetTriple());
326 Triple T(STI.getTargetTriple());
327 uint64_t Features = STI.getFeatureBits();
555 getStreamer().EmitInstruction(TmpInst, STI);
565 getStreamer().EmitInstruction(TmpInst, STI);
573 getStreamer().EmitInstruction(TmpInst, STI);
247 MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI) argument
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp261 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) argument
262 : MipsFrameLowering(STI, STI.stackAlignment()) {}
272 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
287 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
288 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
289 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
290 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
334 if (!STI.isLittle())
357 const TargetRegisterClass *RC = STI
[all...]
H A DMipsSEInstrInfo.cpp363 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); local
365 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
366 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
383 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); local
385 unsigned Size = STI.isABI_N64() ? 64 : 32;
386 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
387 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
388 const TargetRegisterClass *RC = STI.isABI_N64() ?
597 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); local
598 unsigned ADDU = STI
[all...]
/external/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp35 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : argument
36 MCDisassembler(STI, Ctx)
57 const MCSubtargetInfo &STI,
59 return new SparcDisassembler(STI, Ctx);
256 this, STI);
55 createSparcDisassembler( const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp36 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : argument
37 MCDisassembler(STI, Ctx) {}
766 Address, this, STI);
779 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
793 const MCSubtargetInfo &STI,
795 return new XCoreDisassembler(STI, Ctx);
792 createXCoreDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp43 const MCSubtargetInfo &STI; member in class:__anon13910::R600MCCodeEmitter
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
144 createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp674 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, argument
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp31 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI) argument
33 RI(this, &STI), Subtarget(STI) {}
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp43 const MCSubtargetInfo* STI; member in class:__anon25992::ARMAsmBackend
48 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
52 delete STI;
60 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, argument
41 MCDisassembler(STI, Ctx),
42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) argument
61 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
62 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
65 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
66 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
68 return STI.getFeatureBits() & Mips::FeatureMips32r6;
71 bool isGP64() const { return STI
93 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) argument
349 createMipsDisassembler( const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
356 createMipselDisassembler( const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
363 createMips64Disassembler( const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
370 createMips64elDisassembler( const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp74 const MCSubtargetInfo &STI);
112 const MCSubtargetInfo &STI)
117 OutStreamer.EmitInstruction(CallInst, STI);
122 const MCSubtargetInfo &STI)
128 OutStreamer.EmitInstruction(SETHIInst, STI);
133 const MCSubtargetInfo &STI)
140 OutStreamer.EmitInstruction(Inst, STI);
145 const MCSubtargetInfo &STI) {
146 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
151 const MCSubtargetInfo &STI) {
110 EmitCall(MCStreamer &OutStreamer, MCOperand &Callee, const MCSubtargetInfo &STI) argument
120 EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
131 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
143 EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
149 EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) argument
155 EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
162 EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI) argument
175 LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, const MCSubtargetInfo &STI) argument
[all...]
/external/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp80 const MCSubtargetInfo &STI,
83 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
84 switch (STI.getFeatureBits() &
804 const MCSubtargetInfo &STI,
807 return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII));
79 X86GenericDisassembler( const MCSubtargetInfo &STI, MCContext &Ctx, std::unique_ptr<const MCInstrInfo> MII) argument
803 createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument

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