Searched defs:Scale (Results 51 - 75 of 80) sorted by relevance

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/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp393 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); local
455 assert(Scale.getImm() == 1 &&
582 unsigned SS = SSTable[Scale.getImm()];
/external/llvm/lib/Transforms/Scalar/
H A DLoopRerollPass.cpp229 void restrictToScale(uint64_t Scale, argument
238 if (PossibleReds[i].size() % Scale == 0) {
329 bool findScaleFromMul(Instruction *RealIV, uint64_t &Scale,
332 bool collectAllRoots(Loop *L, uint64_t Inc, uint64_t Scale, Instruction *IV,
546 bool LoopReroll::findScaleFromMul(Instruction *RealIV, uint64_t &Scale, argument
595 Scale = MulScaleCI->getZExtValue();
606 // instruction, normally an add, with a positive constant less than Scale. In a
609 // increment (the increment equal to the Scale), and its users in LoopIncs.
610 bool LoopReroll::collectAllRoots(Loop *L, uint64_t Inc, uint64_t Scale, argument
629 if (Idx > 0 && Idx < Scale) {
778 uint64_t Scale = Inc; local
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/external/pdfium/core/include/fxcrt/
H A Dfx_coordinates.h193 void Scale(baseType sx, baseType sy) function in class:CFX_VTemplate
809 void Scale(FX_FLOAT sx, FX_FLOAT sy, FX_BOOL bPrepended = FALSE);
/external/pdfium/core/src/fxcodec/lcms2/lcms2-2.6/src/
H A Dcmscnvrt.c270 cmsMAT3 Scale, m1, m2, m3, m4; local
285 _cmsVEC3init(&Scale.v[0], WhitePointIn->X / WhitePointOut->X, 0, 0);
286 _cmsVEC3init(&Scale.v[1], 0, WhitePointIn->Y / WhitePointOut->Y, 0);
287 _cmsVEC3init(&Scale.v[2], 0, 0, WhitePointIn->Z / WhitePointOut->Z);
293 _cmsMAT3per(&m2, &m1, &Scale);
310 _cmsMAT3per(&m3, &m2, &Scale);
318 if (_cmsMAT3isIdentity(&Scale) && fabs(TempSrc - TempDest) < 0.01) {
/external/libvpx/libvpx/third_party/libyuv/source/
H A Dscale.c1077 // Scale 32 pixels to 12
1110 // Scale 16x3 pixels to 6x1 with interpolation
1174 // Scale 16x2 pixels to 6x1 with interpolation
3046 * Scale plane, 1/2
3091 * Scale plane, 1/4
3135 * Scale plane, 1/8
3175 * Scale plane down, 3/4
3266 * Scale plane, 3/8
3417 * Scale plane down to any dimensions, with interpolation.
3499 * Scale plan
3807 int Scale(const uint8* src_y, const uint8* src_u, const uint8* src_v, function
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/external/libyuv/files/source/
H A Dscale.cc724 // Scale 32 pixels to 12
756 // Scale 16x3 pixels to 6x1 with interpolation
822 // Scale 16x2 pixels to 6x1 with interpolation
2288 * Scale plane, 1/2
2327 * Scale plane, 1/4
2361 * Scale plane, 1/8
2392 * Scale plane down, 3/4
2470 * Scale plane, 3/8
2610 * Scale plane down to any dimensions, with interpolation.
2680 * Scale plan
2985 int Scale(const uint8* src_y, const uint8* src_u, const uint8* src_v, function
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/external/llvm/include/llvm/Analysis/
H A DBlockFrequencyInfoImpl.h218 Scaled64 Scale; member in struct:llvm::BlockFrequencyInfoImplBase::LoopData
/external/llvm/lib/Analysis/
H A DScalarEvolution.cpp1419 const APInt &Scale,
1428 if (Scale != 1 || AccumulatedConstant != 0 || C->getValue()->isZero())
1430 AccumulatedConstant += Scale * C->getValue()->getValue();
1439 Scale * cast<SCEVConstant>(Mul->getOperand(0))->getValue()->getValue();
1466 M.insert(std::make_pair(Ops[i], Scale));
1470 Pair.first->second += Scale;
1557 const SCEV *Scale = getConstant(Ty, Count); variable
1558 const SCEV *Mul = getMulExpr(Scale, Ops[i]);
2037 const SCEV *Scale = getMulExpr(LIOps);
2039 NewOps.push_back(getMulExpr(Scale, AddRe
1415 CollectAddOperandsWithScales(DenseMap<const SCEV *, APInt> &M, SmallVectorImpl<const SCEV *> &NewOps, APInt &AccumulatedConstant, const SCEV *const *Ops, size_t NumOperands, const APInt &Scale, ScalarEvolution &SE) argument
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/external/llvm/lib/CodeGen/
H A DIfConversion.cpp1107 /// Scale down weights to fit into uint32_t. NewTrue is the new weight
1116 uint32_t Scale = (NewMax / UINT32_MAX) + 1; local
1121 MBB->setSuccWeight(SI, (uint32_t)(NewTrue / Scale));
1123 MBB->setSuccWeight(SI, (uint32_t)(NewFalse / Scale));
1125 MBB->setSuccWeight(SI, MBPI->getEdgeWeight(MBB, SI) / Scale);
H A DCodeGenPrepare.cpp1049 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
1082 if (Scale) {
1084 << Scale << "*";
1561 bool MatchScaledValue(Value *ScaleReg, int64_t Scale, unsigned Depth);
1573 /// MatchScaledValue - Try adding ScaleReg*Scale to the current addressing mode.
1576 bool AddressingModeMatcher::MatchScaledValue(Value *ScaleReg, int64_t Scale, argument
1578 // If Scale is 1, then this is the same as adding ScaleReg to the addressing
1580 if (Scale == 1)
1584 if (Scale
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/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp607 unsigned Scale = Log2_32(Size); local
608 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
614 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, MVT::i64);
/external/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp672 unsigned Scale = 1; local
686 Scale = 4;
692 Scale = 2;
696 Scale = 2;
702 Scale = 2;
706 Scale = 2;
711 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
729 unsigned Scale = 1; local
744 Scale = 4;
754 Scale
1702 unsigned Scale = 1; local
1756 unsigned Scale = 1; local
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H A DARMLoadStoreOptimizer.cpp816 unsigned Scale = (MI->getOpcode() == ARM::tSUBspi || local
820 (MI->getOperand(2).getImm() * Scale) == Bytes &&
851 unsigned Scale = (MI->getOpcode() == ARM::tADDspi || local
855 (MI->getOperand(2).getImm() * Scale) == Bytes &&
1887 unsigned Scale = 1; local
1895 Scale = 4;
1899 Scale = 4;
1923 int Limit = (1 << 8) * Scale;
1924 if (OffImm >= Limit || (OffImm <= -Limit) || (OffImm & (Scale-1)))
1933 int Limit = (1 << 8) * Scale;
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H A DARMISelDAGToDAG.cpp163 unsigned Scale);
167 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
304 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
307 static bool isScaledConstantInRange(SDValue Node, int Scale, argument
310 assert(Scale > 0 && "Invalid scale!");
318 if ((ScaledConstant % Scale) != 0)
321 ScaledConstant /= Scale;
603 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
716 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
812 if (isScaledConstantInRange(N, /*Scale
1070 SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset, unsigned Scale) argument
1126 SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base, SDValue &OffImm) argument
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H A DARMBaseInstrInfo.cpp2048 unsigned Scale = 1; local
2082 Scale = 4;
2089 Offset += InstrOffs * Scale;
2090 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2100 int ImmedOffset = Offset / Scale;
2102 if ((unsigned)Offset <= Mask * Scale) {
2128 Offset &= ~(Mask*Scale);
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1643 int Scale = AM.Scale; local
1644 if (Scale < 0) Scale = -Scale;
1645 switch (Scale) {
/external/llvm/lib/Target/Mips/
H A DMipsConstantIslandPass.cpp139 unsigned Bits, Scale; local
143 Scale = 2;
147 Scale = 2;
151 Scale = 2;
155 Scale = 2;
159 Scale = 2;
163 Scale = 2;
167 Scale = 2;
171 Scale = 2;
175 Scale
687 unsigned Scale = 1; local
769 unsigned Scale = 1; local
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/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp147 void Scale(const FAddendCoef& ScaleAmt) { Coeff *= ScaleAmt; } function in class:__anon26243::FAddend
424 Addend0.Scale(Coeff);
427 Addend1.Scale(Coeff);
H A DInstCombineCasts.cpp26 /// X*Scale+Offset.
28 static Value *DecomposeSimpleLinearExpr(Value *Val, unsigned &Scale, argument
32 Scale = 0;
40 Scale = 1;
48 Scale = UINT64_C(1) << RHS->getZExtValue();
55 Scale = RHS->getZExtValue();
67 Scale = SubScale;
74 Scale = 1;
127 unsigned Scale = (AllocElTySize*ArraySizeScale)/CastElTySize; local
129 if (Scale
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H A DInstructionCombining.cpp938 /// Descale - Return a value X such that Val = X * Scale, or null if none. If
940 Value *InstCombiner::Descale(Value *Val, APInt Scale, bool &NoSignedWrap) { argument
943 Scale.getBitWidth() && "Scale not compatible with value!");
945 // If Val is zero or Scale is one then Val = Val * Scale.
946 if (match(Val, m_Zero()) || Scale == 1) {
951 // If Scale is zero then it does not divide Val.
952 if (Scale.isMinValue())
956 // divisible by Scale
1602 uint64_t Scale = SrcSize / ResSize; local
1640 uint64_t Scale = ArrayEltSize / ResSize; local
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/external/llvm/lib/IR/
H A DInstructions.cpp398 Constant *Scale = ConstantExpr::getIntegerCast(CO, IntPtrTy, local
401 AllocSize = ConstantExpr::getMul(Scale, cast<Constant>(AllocSize));
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp253 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon26165::X86AsmParser::IntelExprStateMachine
263 Scale(1), Imm(imm), Sym(nullptr), StopOnLBrac(stoponlbrac),
268 unsigned getScale() { return Scale; }
362 Scale = 1;
399 Scale = 1;
432 // Index Register - Scale * Register
437 // Get the scale and replace the 'Scale * Register' with '0'.
438 Scale = IC.popOperand();
482 // Index Register - Register * Scale
485 Scale
978 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1247 int Scale = SM.getScale(); local
1770 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
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/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp626 // Now construct the final address. Note that the Disp, Scale,
641 assert(AM.Scale == 1 && "Scale with no index!");
727 unsigned Scale = AM.Scale; local
762 Scale = S;
778 AM.Scale = Scale;
919 assert(AM.Scale == 1 && "Scale wit
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H A DX86ISelDAGToDAG.cpp60 unsigned Scale; member in struct:__anon26191::X86ISelAddressMode
73 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
112 << " Scale" << Scale << '\n' local
206 SDValue &Scale, SDValue &Index, SDValue &Disp,
210 SDValue &Scale, SDValue &Index, SDValue &Disp,
213 SDValue &Scale, SDValue &Index, SDValue &Disp,
216 SDValue &Scale, SDValue &Index, SDValue &Disp,
219 SDValue &Base, SDValue &Scale,
225 SDValue &Base, SDValue &Scale,
237 getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1310 SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1355 SelectScalarSSELoad(SDNode *Root, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment, SDValue &PatternNodeWithChain) argument
1422 SelectLEA64_32Addr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1461 SelectLEAAddr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1523 SelectTLSADDRAddr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1547 TryFoldLoad(SDNode *P, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
2036 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6)); local
2725 SDValue Base, Scale, Index, Disp, Segment; local
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/external/llvm/lib/Transforms/Instrumentation/
H A DAddressSanitizer.cpp299 /// shadow = (mem >> Scale) ADD-or-OR Offset.
301 int Scale; member in struct:__anon26249::ShadowMapping
342 Mapping.Scale = kDefaultShadowScale;
344 Mapping.Scale = ClMappingScale;
432 return RedzoneSizeForScale(Mapping.Scale);
490 StackAlignment(1 << Mapping.Scale) {}
626 Shadow = IRB.CreateLShr(Shadow, Mapping.Scale);
766 unsigned Granularity = 1 << Mapping.Scale;
820 size_t Granularity = 1 << Mapping.Scale;
850 *C, std::max(8U, TypeSize >> Mapping.Scale));
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