| /external/llvm/lib/Transforms/Instrumentation/ |
| H A D | MemorySanitizer.cpp | 1646 Value *Shift = IRB.CreateBinOp(I.getOpcode(), S1, V2); local
1647 setShadow(&I, IRB.CreateOr(Shift, S2Conv));
1976 Value *Shift = IRB.CreateCall2(I.getCalledValue(), local
1978 Shift = IRB.CreateBitCast(Shift, getShadowTy(&I));
1979 setShadow(&I, IRB.CreateOr(Shift, S2Conv));
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| /external/valgrind/main/VEX/priv/ |
| H A D | host_arm_defs.h | 641 } Shift; member in union:__anon31854::__anon31855
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 3187 "Shift operators return type must be the same as their first arg");
3336 unsigned Shift = ElementSize * N2C->getZExtValue(); local
3337 APInt ShiftedVal = C->getAPIntValue().lshr(Shift);
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| H A D | DAGCombiner.cpp | 370 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
3442 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { argument
3453 Shift = Op;
4079 SDValue Shift; local
4082 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4086 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4089 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4199 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT, local
4202 Shift);
4689 SDValue Shift local
8088 unsigned Shift; member in struct:__anon25800::LoadedSlice::Cost
8165 unsigned Shift; member in struct:__anon25800::LoadedSlice
8193 UsedBits <<= Shift; local
8539 unsigned Shift = 0; local
11218 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), local
11230 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), local
11382 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType, local
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4053 // Shift the second operand right to 32 bits.
4057 // Shift the first operand left to 32 bits.
4594 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0; local
4600 unsigned ShAmt = (i << Shift) % 8;
9131 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9132 while ((1U << Shift) < NumElems) {
9133 if (SVOp->getMaskElt(1U << Shift) == 1)
9135 Shift += 1;
9137 if (Shift > 3)
9142 unsigned Mask = (1U << Shift)
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| H A D | constants-arm64.h | 332 enum Shift { enum in namespace:v8::internal
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5040 SDValue Shift = N->getOperand(1);
5043 unsigned ShiftOpc = Shift.getOpcode();
5049 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5069 SDValue Y = Shift.getOperand(0);
5075 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
6319 unsigned Shift = (63 - LZ) / 16; local
6321 return (Shift < 3) ? true : false;
6722 SDValue Shift = N->getOperand(2); local
6742 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
|
| /external/vixl/src/a64/ |
| H A D | constants-a64.h | 222 enum Shift { enum in namespace:vixl
|
| /external/clang/lib/Sema/ |
| H A D | SemaExpr.cpp | 9612 Expr *SubExpr, StringRef Shift) {
9617 << Bop->getSourceRange() << OpLoc << Shift << Op;
9676 StringRef Shift = BinaryOperator::getOpcodeStr(Opc); local
9677 DiagnoseAdditionInShift(Self, OpLoc, LHSExpr, Shift);
9678 DiagnoseAdditionInShift(Self, OpLoc, RHSExpr, Shift);
9611 DiagnoseAdditionInShift(Sema &S, SourceLocation OpLoc, Expr *SubExpr, StringRef Shift) argument
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