Searched defs:TT (Results 51 - 75 of 96) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp48 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, argument
53 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
54 Subtarget(TT, CPU, FS, *this, isLittle, Options) {
73 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, argument
77 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
86 ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT, argument
91 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
95 ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT, argument
100 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
104 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, argument
116 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
125 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
[all...]
H A DARMSubtarget.cpp151 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, argument
154 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
156 TargetTriple(TT), Options(Options), TargetABI(ARM_ABI_UNKNOWN),
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp397 StringRef TT,
399 return new MipsAsmBackend(T, Triple(TT).getOS(),
405 StringRef TT,
407 return new MipsAsmBackend(T, Triple(TT).getOS(),
413 StringRef TT,
415 return new MipsAsmBackend(T, Triple(TT).getOS(),
421 StringRef TT,
423 return new MipsAsmBackend(T, Triple(TT).getOS(),
395 createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
403 createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
411 createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
419 createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
H A DMipsMCTargetDesc.cpp46 static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) { argument
48 Triple TheTriple(TT);
64 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) { argument
70 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, argument
72 CPU = selectMipsCPU(TT, CPU);
74 InitMipsMCSubtargetInfo(X, TT, CPU, FS);
78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument
79 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
88 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
109 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, argument
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsSubtarget.cpp63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) { argument
65 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, argument
108 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
117 TargetTriple(TT),
170 if (TT.find("linux") == std::string::npos)
H A DMipsTargetMachine.cpp53 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT, argument
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 Subtarget(TT, CPU, FS, isLittle, RM, this) {
66 MipsebTargetMachine(const Target &T, StringRef TT, argument
70 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
75 MipselTargetMachine(const Target &T, StringRef TT, argument
79 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
/external/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp69 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT, argument
74 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
75 Subtarget(TT, CPU, FS, *this, is64bit) {
82 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
85 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
90 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
93 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
81 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
89 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.cpp77 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, argument
80 : PPCGenSubtargetInfo(TT, CPU, FS), IsPPC64(is64Bit), TargetTriple(TT),
H A DPPCTargetMachine.cpp40 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, argument
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, *this, is64Bit, OL) {
51 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, argument
56 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
61 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, argument
66 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
H A DPPCCTRLoops.cpp105 bool mightUseCTR(const Triple &TT, BasicBlock *BB);
197 bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicBlock *BB) { argument
363 isLargeIntegerTy(TT.isArch32Bit(), CI->getSrcTy()->getScalarType()) ||
364 isLargeIntegerTy(TT.isArch32Bit(), CI->getDestTy()->getScalarType()))
366 } else if (isLargeIntegerTy(TT.isArch32Bit(),
373 } else if (TT.isArch32Bit() &&
401 Triple TT = Triple(L->getHeader()->getParent()->getParent()-> local
403 if (!TT.isArch32Bit() && !TT.isArch64Bit())
429 if (mightUseCTR(TT, *
[all...]
/external/llvm/lib/Target/R600/
H A DAMDGPUTargetMachine.cpp66 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, argument
73 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
74 Subtarget(TT, CPU, FS),
/external/llvm/lib/Target/R600/MCTargetDesc/
H A DAMDGPUMCTargetDesc.cpp44 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { argument
50 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, argument
53 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
57 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
85 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, argument
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.cpp98 StringRef TT) {
99 MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
114 static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) { argument
120 static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, argument
124 InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
128 static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
184 static MCStreamer *createSystemZMCObjectStreamer(const Target &T, StringRef TT, argument
/external/llvm/lib/Target/X86/
H A DX86Subtarget.cpp345 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, argument
348 : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
349 PICStyle(PICStyles::None), TargetTriple(TT),
H A DX86TargetMachine.cpp34 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, argument
38 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
39 Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUAsmBackend.cpp73 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, StringRef TT) { argument
H A DAMDGPUMCTargetDesc.cpp43 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { argument
49 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, argument
52 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
56 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
83 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, argument
/external/clang/lib/CodeGen/
H A DCodeGenTypes.cpp191 const TagType *TT = Ty->getAs<TagType>(); local
192 if (!TT) return true;
195 if (TT->isIncompleteType())
199 const RecordType *RT = dyn_cast<RecordType>(TT);
/external/clang/lib/StaticAnalyzer/Checkers/
H A DLLVMConventionsChecker.cpp55 const TypedefType *TT = T->getAs<TypedefType>(); local
56 if (!TT)
59 const TypedefNameDecl *TD = TT->getDecl();
H A DNSErrorChecker.cpp307 const TypedefType* TT = PPT->getPointeeType()->getAs<TypedefType>(); local
308 if (!TT) return false;
310 return TT->getDecl()->getIdentifier() == II;
/external/clang/test/CodeGenCXX/
H A Dtemp-order.cpp21 TempTracker &TT; member in struct:A
26 : TT(_TT), P(_P), Truth(_Truth) {}
27 A(const A &RHS) : TT(RHS.TT), P(RHS.P), Truth(RHS.Truth) { RHS.P = 0; }
30 TT.Product *= pow(P, ++TT.Index);
34 TT = RHS.TT;
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp84 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { argument
85 Triple triple(TT);
89 unsigned Len = TT.size();
95 if (Len >= 5 && TT.substr(0, 4) == "armv")
97 else if (Len >= 7 && TT.substr(0, 6) == "armebv")
99 else if (Len >= 7 && TT.substr(0, 6) == "thumbv")
101 else if (Len >= 9 && TT.substr(0, 8) == "thumbebv")
107 unsigned SubVer = TT[Idx];
119 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
127 } else if (Len >= Idx+3 && TT[Id
193 createARMMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
220 createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
256 createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
270 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
306 createARMMCRelocationInfo(StringRef TT, MCContext &Ctx) argument
[all...]
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp50 static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) { argument
51 Triple TheTriple(TT);
62 static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, argument
65 InitPPCMCSubtargetInfo(X, TT, CPU, FS);
69 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument
70 Triple TheTriple(TT);
89 static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
95 Triple T(TT);
102 Triple T(TT);
157 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, argument
[all...]
/external/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.cpp37 StringRef TT) {
38 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
46 StringRef TT) {
47 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
60 static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) { argument
66 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, argument
69 Triple TheTriple(TT);
72 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
87 static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
104 static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Relo argument
36 createSparcMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
45 createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
125 createMCStreamer(const Target &T, StringRef TT, MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
[all...]
/external/llvm/lib/Target/
H A DTargetMachine.cpp36 StringRef TT, StringRef CPU, StringRef FS,
38 : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS),
35 TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options) argument

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