/external/llvm/lib/CodeGen/ |
H A D | ProcessImplicitDefs.cpp | 30 MachineRegisterInfo *MRI; member in class:__anon25785::ProcessImplicitDefs 83 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { 143 MRI = &MF.getRegInfo(); 144 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
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H A D | LiveRangeCalc.h | 38 const MachineRegisterInfo *MRI; member in class:llvm::LiveRangeCalc 128 LiveRangeCalc() : MF(nullptr), MRI(nullptr), Indexes(nullptr),
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H A D | RegAllocFast.cpp | 58 MachineRegisterInfo *MRI; member in class:__anon25790::RAFast 227 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg()); 230 return ++I == MRI->reg_nodbg_end(); 288 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg); 516 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); 520 !RC->contains(Hint) || !MRI->isAllocatable(Hint))) 593 MRI->hasOneNonDBGUse(VirtReg)) { 594 const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg); 626 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); 797 if (MRI [all...] |
H A D | TailDuplication.cpp | 67 MachineRegisterInfo *MRI; member in class:__anon25829::TailDuplicatePass 140 MRI = &MF.getRegInfo(); 144 PreRegAlloc = MRI->isSSA(); 146 if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF)) 250 MachineInstr *DefMI = MRI->getVRegDef(VReg); 267 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg); 268 while (UI != MRI->use_end()) { 298 if (MRI->hasOneNonDBGUse(Src) && 299 MRI->constrainRegClass(Src, MRI 343 isDefLiveOut(unsigned Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIInstrInfo.h | 29 MachineRegisterInfo &MRI, 35 MachineRegisterInfo &MRI, 43 MachineRegisterInfo &MRI, 148 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
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H A D | SILowerI1Copies.cpp | 72 MachineRegisterInfo &MRI = MF.getRegInfo(); local 112 MRI.getRegClass(MI.getOperand(0).getReg()); 114 MRI.getRegClass(MI.getOperand(1).getReg()); 145 MRI.setRegClass(Reg, &AMDGPU::VReg_32RegClass);
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H A D | SIMachineFunctionInfo.h | 50 unsigned reserveLanes(MachineRegisterInfo &MRI, MachineFunction *MF,
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H A D | R600MachineScheduler.h | 32 MachineRegisterInfo *MRI; member in class:llvm::R600SchedStrategy 71 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
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H A D | SIFixSGPRLiveRanges.cpp | 75 MachineRegisterInfo &MRI = MF.getRegInfo(); local 95 const TargetRegisterClass *RC = MRI.getRegClass(Def.getReg());
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/external/llvm/tools/llvm-mc/ |
H A D | Disassembler.cpp | 165 std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(Triple)); 166 if (!MRI) { 171 std::unique_ptr<const MCAsmInfo> MAI(T.createMCAsmInfo(*MRI, Triple)); 178 MCContext Ctx(MAI.get(), MRI.get(), nullptr);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.h | 42 MachineRegisterInfo & MRI, unsigned dword_offset) const;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.cpp | 68 const MCRegisterInfo &MRI, 70 return new AMDGPUInstPrinter(MAI, MII, MRI); 64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/include/llvm/MC/ |
H A D | MCInstPrinter.h | 41 const MCRegisterInfo &MRI; member in class:llvm::MCInstPrinter 60 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri),
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/external/llvm/lib/MC/MCDisassembler/ |
H A D | Disassembler.cpp | 46 const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple); local 47 if (!MRI) 51 const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple); 68 MCContext *Ctx = new MCContext(MAI, MRI, nullptr); 89 *MAI, *MII, *MRI, *STI); 95 TheTarget, MAI, MRI, 333 const MCRegisterInfo *MRI = DC->getRegisterInfo(); local 338 AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
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/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.h | 81 const MCRegisterInfo &MRI) 82 : MCInstPrinter(MAI, MII, MRI) {} 80 MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
H A D | NVPTXMCTargetDesc.cpp | 65 const MCRegisterInfo &MRI, 68 return new NVPTXInstPrinter(MAI, MII, MRI, STI); 61 createNVPTXMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.h | 27 const MCRegisterInfo &MRI, bool isDarwin) 28 : MCInstPrinter(MAI, MII, MRI), IsDarwin(isDarwin) {} 26 PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, bool isDarwin) argument
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/external/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.h | 26 const MCRegisterInfo &MRI) 27 : MCInstPrinter(MAI, MII, MRI) {} 25 SystemZInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.cpp | 68 const MCRegisterInfo &MRI, 70 return new AMDGPUInstPrinter(MAI, MII, MRI); 64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 36 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, argument 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 45 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, argument 48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 152 const MCRegisterInfo &MRI, 154 return new SparcInstPrinter(MAI, MII, MRI, STI); 148 createSparcMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/X86/ |
H A D | X86VZeroUpper.cpp | 108 static bool checkFnHasLiveInYmm(MachineRegisterInfo &MRI) { argument 109 for (MachineRegisterInfo::livein_iterator I = MRI.livein_begin(), 110 E = MRI.livein_end(); I != E; ++I) 254 MachineRegisterInfo &MRI = MF.getRegInfo(); local 264 if (!MRI.reg_nodbg_empty(*i)) { 285 if (checkFnHasLiveInYmm(MRI))
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/external/llvm/include/llvm/Support/ |
H A D | TargetRegistry.h | 82 typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI, 105 const MCRegisterInfo &MRI, 120 const MCRegisterInfo &MRI, 123 const MCRegisterInfo &MRI, 283 MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, argument 287 return MCAsmInfoCtorFn(MRI, Triple); 361 MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, argument 365 return MCAsmBackendCtorFn(*this, MRI, Triple, CPU); 400 const MCRegisterInfo &MRI, 404 return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, ST 397 createMCInstPrinter(unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) const argument 409 createMCCodeEmitter(const MCInstrInfo &II, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) const argument 1088 Allocator(const Target &T, const MCRegisterInfo &MRI, StringRef Triple, StringRef CPU) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 222 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 223 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 244 if (PairedPhys && MRI.isReserved(PairedPhys)) 260 if (!Paired || MRI.isReserved(Paired)) 269 MachineRegisterInfo *MRI = &MF.getRegInfo(); local 270 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 279 Hint = MRI->getRegAllocationHint(OtherReg); 282 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 341 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 353 if (!MRI 593 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 121 const MachineRegisterInfo *MRI = local 123 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || 124 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); 600 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 602 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 636 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 638 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 673 if (MRI 1619 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 1889 IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, MachineRegisterInfo &MRI) argument 1900 IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) argument 1904 IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) argument 1908 IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) argument 1916 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local [all...] |
/external/clang/tools/driver/ |
H A D | cc1as_main.cpp | 304 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(Opts.Triple)); 305 assert(MRI && "Unable to create target register info!"); 307 std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, Opts.Triple)); 325 MCContext Ctx(MAI.get(), MRI.get(), MOFI.get(), &SrcMgr); 360 TheTarget->createMCInstPrinter(Opts.OutputAsmVariant, *MAI, *MCII, *MRI, 365 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); 366 MAB = TheTarget->createMCAsmBackend(*MRI, Opts.Triple, Opts.CPU); 377 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); 378 MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, Opts.Triple,
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