/external/libcxx/test/utilities/time/time.clock/time.clock.system/ |
H A D | rep_signed.pass.cpp | 22 std::chrono::system_clock::duration::zero());
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/external/libcxx/test/utilities/time/time.duration/time.duration.special/ |
H A D | zero.pass.cpp | 14 // static constexpr duration zero(); 26 Rep zero_rep = std::chrono::duration_values<Rep>::zero(); 27 assert(D::zero().count() == zero_rep); 32 constexpr Rep zero_rep = std::chrono::duration_values<Rep>::zero(); 33 static_assert(D::zero().count() == zero_rep, "");
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/external/srec/config/en.us/tcp/ |
H A D | change_sample_rate2.tcp | 12 recognize_nist dallas/0000/S072.nwf 0 0 oh eight four zero nine two five one eight five 14 recognize_nist dallas/0000/S075.nwf 0 0 zero seven six five nine oh zero two five two 15 recognize_nist dallas/0000/S076.nwf 0 0 five zero two seven four nine three three zero zero 16 recognize_nist dallas/0000/S077.nwf 0 0 six nine five zero two eight seven seven three six 17 recognize_nist dallas/0000/S079.nwf 0 0 seven one one five six zero oh six five nine 18 recognize_nist dallas/0000/S080.nwf 0 0 seven oh three seven nine zero six eight five seven 19 recognize_nist dallas/0000/S083.nwf 0 0 zero nin [all...] |
/external/llvm/test/MC/Mips/ |
H A D | mips-register-names-o32.s | 4 # Second byte of addiu with $zero at rt contains the number of the source 8 addiu $zero, $zero, 0 # CHECK: encoding: [0x24,0x00,0x00,0x00] 9 addiu $at, $zero, 0 # CHECK: encoding: [0x24,0x01,0x00,0x00] 10 addiu $v0, $zero, 0 # CHECK: encoding: [0x24,0x02,0x00,0x00] 11 addiu $v1, $zero, 0 # CHECK: encoding: [0x24,0x03,0x00,0x00] 12 addiu $a0, $zero, 0 # CHECK: encoding: [0x24,0x04,0x00,0x00] 13 addiu $a1, $zero, 0 # CHECK: encoding: [0x24,0x05,0x00,0x00] 14 addiu $a2, $zero, 0 # CHECK: encoding: [0x24,0x06,0x00,0x00] 15 addiu $a3, $zero, [all...] |
H A D | mips64-register-names-o32.s | 5 # Second byte of daddiu with $zero at rt contains the number of the source 9 daddiu $zero, $zero, 0 # CHECK: encoding: [0x64,0x00,0x00,0x00] 10 daddiu $at, $zero, 0 # CHECK: encoding: [0x64,0x01,0x00,0x00] 11 daddiu $v0, $zero, 0 # CHECK: encoding: [0x64,0x02,0x00,0x00] 12 daddiu $v1, $zero, 0 # CHECK: encoding: [0x64,0x03,0x00,0x00] 13 daddiu $a0, $zero, 0 # CHECK: encoding: [0x64,0x04,0x00,0x00] 14 daddiu $a1, $zero, 0 # CHECK: encoding: [0x64,0x05,0x00,0x00] 15 daddiu $a2, $zero, 0 # CHECK: encoding: [0x64,0x06,0x00,0x00] 16 daddiu $a3, $zero, [all...] |
H A D | micromips-el-fixup-data.s | 19 # CHECK: 09 b4 04 00 bne $9, $zero, 8 21 addu $zero, $zero, $zero
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/external/oprofile/events/mips/r10000/ |
H A D | events | 6 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles 7 event:0x01 counters:0 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued 8 event:0x01 counters:1 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated 9 event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued 10 event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated 11 event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued 12 event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated 13 event:0x04 counters:0 um:zero minimum:500 name:STORE_COND_ISSUED : Store conditional issued 14 event:0x04 counters:1 um:zero minimum:500 name:STORE_COND_GRADUATED : Store conditional graduated 15 event:0x05 counters:0 um:zero minimu [all...] |
/external/oprofile/events/mips/r12000/ |
H A D | events | 4 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles 5 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:DECODED_INSTRUCTIONS : Decoded instructions 6 event:0x2 counters:0,1,2,3 um:zero minimum:500 name:DECODED_LOADS : Decoded loads 7 event:0x3 counters:0,1,2,3 um:zero minimum:500 name:DECODED_STORES : Decoded stores 8 event:0x4 counters:0,1,2,3 um:zero minimum:500 name:MISS_TABLE_OCCUPANCY : Miss Handling Table Occupancy 9 event:0x5 counters:0,1,2,3 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional 10 event:0x6 counters:0,1,2,3 um:zero minimum:500 name:RESOLVED_BRANCH_CONDITIONAL : Resolved conditional branches 11 event:0x7 counters:0,1,2,3 um:zero minimum:500 name:QUADWORRDS_WRITEBACK_FROM_SC : Quadwords written back from secondary cache 12 event:0x8 counters:0,1,2,3 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS : Correctable ECC errors on secondary cache data 13 event:0x9 counters:0,1,2,3 um:zero minimu [all...] |
/external/oprofile/events/mips/rm7000/ |
H A D | events | 4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles 5 event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Total instructions issued 6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued 7 event:0x03 counters:0,1 um:zero minimum:500 name:INTEGER_INSTRUCTIONS_ISSUED : Integer instructions issued 8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued 9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued 10 event:0x06 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual issued pairs 11 event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_PREFETCHES : Branch prefetches 12 event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses 13 event:0x09 counters:0,1 um:zero minimu [all...] |
/external/oprofile/events/mips/24K/ |
H A D | events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles 15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses 21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted) 22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed 23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict) 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses 25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses 26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses 27 event:0x8 counters:0 um:zero minimu [all...] |
/external/oprofile/events/mips/vr5432/ |
H A D | events | 4 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock) 5 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated 6 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync) 7 event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Store execution 8 event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers) 9 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores 10 event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores) 11 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills 12 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses) 13 event:0x9 counters:0,1 um:zero minimu [all...] |
/external/oprofile/events/mips/vr5500/ |
H A D | events | 6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles 7 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed 8 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction 9 event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction 10 event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction 11 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction 12 event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory 13 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill 14 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss 15 event:0x9 counters:0,1 um:zero minimu [all...] |
/external/oprofile/events/mips/rm9000/ |
H A D | events | 4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles 5 event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued 6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued 7 event:0x03 counters:0,1 um:zero minimum:500 name:INT_INSTRUCTIONS_ISSUED : Integer instructions issued 8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued 9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued 10 event:0x06 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_DUAL_ISSUED : Dual-issued instruction pairs 11 event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions 12 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles 13 event:0x0a counters:0,1 um:zero minimu [all...] |
/external/oprofile/events/mips/1004K/ |
H A D | events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles 15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses 21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted) 22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed 23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict) 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses 25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses 26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses 27 event:0x8 counters:0 um:zero minimu [all...] |
/external/oprofile/events/mips/20K/ |
H A D | events | 6 event:0x0 counters:0 um:zero minimum:500 name:CYCLES : CPU cycles 7 event:0x1 counters:0 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions 8 event:0x2 counters:0 um:zero minimum:500 name:FETCH_GROUPS : Fetch groups entering CPU execution pipes 9 event:0x3 counters:0 um:zero minimum:500 name:FP_INSNS_COMPLETED : Instructions completed in FPU datapath (computational event:instructions only) 10 event:0x4 counters:0 um:zero minimum:500 name:TLB_REFILLS_TAKEN : Taken TLB refill exceptions 11 event:0x5 counters:0 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution 12 event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution 13 event:0x7 counters:0 um:zero minimum:500 name:JTLB_EXCEPTIONS : Taken Joint-TLB exceptions 14 event:0x8 counters:0 um:zero minimum:500 name:REPLAY_DUE_TO_LOAD_DEPENDENT_SPEC_DISPATCH : Replays due to load-dependent speculative dispatch 15 event:0x9 counters:0 um:zero minimu [all...] |
/external/chromium_org/v8/test/mjsunit/ |
H A D | smi-negative-zero.js | 30 var zero = 0; variable 40 assertEquals(-Infinity, one / (-zero), "one / -0 I"); 42 assertEquals(-Infinity, one / (zero * minus_one), "one / -1"); 43 assertEquals(-Infinity, one / (minus_one * zero), "one / -0 II"); 44 assertEquals(Infinity, one / (zero * zero), "one / 0 I"); 47 assertEquals(-Infinity, one / (zero / minus_one), "one / -0 III"); 48 assertEquals(Infinity, one / (zero / one), "one / 0 II"); 58 assertEquals(-Infinity, one / (-1 * zero), "bar2"); 59 assertEquals(Infinity, one / (0 * zero), "bar [all...] |
H A D | keyed-call-generic.js | 72 function zero () { return 0; } function 76 var fixed_array = [zero, one, two]; 78 var dict_array = [ zero, one, two ]; 81 var fast_prop = { zero: zero, one: one, two: two }; 83 var normal_prop = { zero: zero, one: one, two: two }; 88 var first3str = ['zero', 'one', 'two']; 113 testException([zero, one, /* hole */ ], [0, 1, 2], [false, false, true]);
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/external/libcxx/test/language.support/support.limits/limits/numeric.limits.members/ |
H A D | infinity.pass.cpp | 28 extern float zero; 53 test<float>(1./zero); 54 test<double>(1./zero); 55 test<long double>(1./zero); 58 float zero = 0; variable
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/external/oprofile/events/mips/25K/ |
H A D | events | 6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : CPU cycles 7 event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions 8 event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued 9 event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued 10 event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued 11 event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued 12 event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued 13 event:0x7 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual-issued pairs 14 event:0x8 counters:0,1 um:zero minimum:500 name:INSNS_COMPLETE : Instruction that completed execution (with or without exception) 15 event:0x9 counters:0,1 um:zero minimu [all...] |
/external/chromium_org/third_party/WebKit/Source/platform/audio/ |
H A D | ZeroPole.cpp | 41 float zero = m_zero; local 45 const float k1 = 1 / (1 - zero); 56 float output1 = k1 * (input - zero * lastX);
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/external/chromium_org/net/base/ |
H A D | int128_unittest.cc | 12 uint128 zero(0); 43 EXPECT_EQ(one, one | zero); 46 EXPECT_EQ(zero, one & zero); 47 EXPECT_EQ(zero, big & ~big); 48 EXPECT_EQ(zero, one ^ one); 49 EXPECT_EQ(zero, big ^ big); 50 EXPECT_EQ(one, one ^ zero); 58 EXPECT_EQ(zero, (one >> 80) << 80); 59 EXPECT_EQ(zero, bi [all...] |
/external/llvm/autoconf/m4/ |
H A D | need_dev_zero_for_mmap.m4 | 2 # When allocating RWX memory, check whether we need to use /dev/zero 6 [AC_CACHE_CHECK([if /dev/zero is needed for mmap], 16 [Define if /dev/zero should be used when mapping RWX memory, or undefine if its not necessary])
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/external/compiler-rt/test/asan/TestCases/Linux/ |
H A D | coverage.cc | 38 static volatile char *zero = 0; local 39 *zero = 0; // SEGV if argc == 5.
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/external/compiler-rt/test/asan/TestCases/ |
H A D | large_func_test.cc | 9 static void LargeFunction(int *x, int zero) { argument 24 x[zero + 103]++; // we should report this exact line
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/external/jemalloc/include/jemalloc/internal/ |
H A D | chunk_mmap.h | 14 void *chunk_alloc_mmap(size_t size, size_t alignment, bool *zero);
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