Searched defs:MO (Results 76 - 100 of 147) sorted by relevance

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/external/llvm/lib/CodeGen/AsmPrinter/
H A DEHStreamer.cpp165 const MachineOperand &MO = MI->getOperand(I); local
167 if (!MO.isGlobal()) continue;
169 const Function *F = dyn_cast<Function>(MO.getGlobal());
/external/llvm/lib/CodeGen/
H A DMachineCSE.cpp119 MachineOperand &MO = MI->getOperand(i); local
120 if (!MO.isReg() || !MO.isUse())
122 unsigned Reg = MO.getReg();
143 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
156 MO.setReg(SrcReg);
182 const MachineOperand &MO = I->getOperand(i); local
183 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
185 if (!MO
216 const MachineOperand &MO = MI->getOperand(i); local
235 const MachineOperand &MO = MI->getOperand(i); local
307 const MachineOperand &MO = I->getOperand(i); local
394 const MachineOperand &MO = MI->getOperand(i); local
526 MachineOperand &MO = MI->getOperand(i); local
[all...]
H A DMachineSink.cpp175 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
176 MachineInstr *UseInst = MO.getParent();
177 unsigned OpNo = &MO - &UseInst->getOperand(0);
188 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
190 MachineInstr *UseInst = MO.getParent();
191 unsigned OpNo = &MO - &UseInst->getOperand(0);
302 const MachineOperand &MO = MI->getOperand(i); local
303 if (!MO.isReg() || !MO.isUse())
305 unsigned Reg = MO
490 const MachineOperand &MO = MI->getOperand(i); local
619 const MachineOperand &MO = MI->getOperand(I); local
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H A DPrologEpilogInserter.cpp871 MachineOperand &MO = MI->getOperand(i); local
872 unsigned Reg = MO.getReg();
H A DExecutionDepsFix.cpp509 MachineOperand &MO = MI->getOperand(i); local
510 if (!MO.isReg())
512 if (MO.isImplicit())
514 if (MO.isUse())
516 int rx = regIndex(MO.getReg());
H A DLiveVariables.cpp215 MachineOperand &MO = LastDef->getOperand(i); local
216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
218 unsigned DefReg = MO.getReg();
376 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg); local
377 if (MO) {
379 assert(!MO->isDead());
403 MachineOperand *MO = local
405 bool NeedEC = MO
422 HandleRegMask(const MachineOperand &MO) argument
565 MachineOperand &MO = MI->getOperand(i); local
686 MachineOperand &MO = MI->getOperand(i); local
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H A DPeepholeOptimizer.cpp505 const MachineOperand &MO = Copy.getOperand(OpIdx); local
506 if (!MO.isReg() || !MO.getReg())
508 if (MO.isDef())
648 MachineOperand &MO = MI->getOperand(i); local
649 if (!MO.isReg() || MO.isDef())
651 unsigned Reg = MO.getReg();
820 const MachineOperand &MO = Def->getOperand(OpIdx); local
821 if (!MO
1009 const MachineOperand &MO = Def->getOperand(SrcIdx); local
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H A DRegAllocFast.cpp217 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
220 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) { argument
223 if (StackSlotForVirtReg[MO.getReg()] != -1)
226 // Check that the use/def chain has exactly one operand - MO.
227 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
228 if (&*I != &MO)
236 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
237 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
238 if (MO.getReg() == LR.PhysReg)
239 MO
345 usePhysReg(MachineOperand &MO) argument
623 MachineOperand &MO = MI->getOperand(OpNum); local
668 MachineOperand &MO = MI->getOperand(OpNum); local
701 MachineOperand &MO = MI->getOperand(i); local
717 MachineOperand &MO = MI->getOperand(i); local
731 MachineOperand &MO = MI->getOperand(i); local
756 MachineOperand &MO = MI->getOperand(i); local
772 MachineOperand &MO = MI->getOperand(i); local
847 MachineOperand &MO = MI->getOperand(i); local
908 MachineOperand &MO = MI->getOperand(i); local
963 MachineOperand &MO = MI->getOperand(i); local
985 MachineOperand &MO = MI->getOperand(i); local
1013 MachineOperand &MO = MI->getOperand(i); local
[all...]
H A DStackColoring.cpp254 const MachineOperand &MO = MI.getOperand(0); local
255 unsigned Slot = MO.getIndex();
534 for (MachineOperand &MO : I.operands()) {
535 if (!MO.isFI())
537 int FromSlot = MO.getIndex();
568 MO.setIndex(ToSlot);
595 for (const MachineOperand &MO : I.operands()) {
596 if (!MO.isFI())
599 int Slot = MO.getIndex();
H A DTailDuplication.cpp434 MachineOperand &MO = NewMI->getOperand(i); local
435 if (!MO.isReg())
437 unsigned Reg = MO.getReg();
440 if (MO.isDef()) {
443 MO.setReg(NewReg);
450 MO.setReg(VI->second);
475 MachineOperand &MO = II->getOperand(i+1); local
476 if (MO.getMBB() == FromBB) {
490 MachineOperand &MO = II->getOperand(i+1); local
491 if (MO
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H A DTargetInstrInfo.cpp227 MachineOperand &MO = MI->getOperand(i); local
228 if (MO.isReg()) {
229 MO.setReg(Pred[j].getReg());
231 } else if (MO.isImm()) {
232 MO.setImm(Pred[j].getImm());
234 } else if (MO.isMBB()) {
235 MO.setMBB(Pred[j].getMBB());
416 MachineOperand &MO = MI->getOperand(i); local
422 MF.getRegInfo().getRegClass(MO.getReg());
423 bool Valid = TII.getStackSlotRange(RC, MO
499 const MachineOperand &MO = MI->getOperand(1-Ops[0]); local
606 const MachineOperand &MO = MI->getOperand(i); local
[all...]
H A DTargetLoweringBase.cpp934 MachineOperand &MO = MI->getOperand(OperIdx); local
935 if (!MO.isFI())
940 int FI = MO.getIndex();
/external/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp139 void maybeKillChain(MachineOperand &MO, unsigned Idx,
548 MachineOperand &MO = I->getOperand(0); local
550 bool Change = TransformAll || getColor(MO.getReg()) != C;
555 Substs[MO.getReg()] = Reg;
556 MO.setReg(Reg);
656 maybeKillChain(MachineOperand &MO, unsigned Idx, argument
660 MachineInstr *MI = MO.getParent();
662 if (MO.isReg()) {
665 if (MO.isKill() && ActiveChains.find(MO
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H A DAArch64AsmPrinter.cpp66 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const { argument
67 return MCInstLowering.lowerOperand(MO, MCOp);
94 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
95 bool printAsmRegInClass(const MachineOperand &MO,
211 const MachineOperand &MO = MI->getOperand(OpNum); local
212 switch (MO.getType()) {
216 unsigned Reg = MO.getReg();
218 assert(!MO.getSubReg() && "Subregs should be eliminated!");
223 int64_t Imm = MO.getImm();
230 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, cha argument
251 printAsmRegInClass(const MachineOperand &MO, const TargetRegisterClass *RC, bool isVector, raw_ostream &O) argument
268 const MachineOperand &MO = MI->getOperand(OpNum); local
353 const MachineOperand &MO = MI->getOperand(OpNum); local
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H A DAArch64LoadStoreOptimizer.cpp343 MachineOperand &MO = MI->getOperand(i); local
344 if (MO.isRegMask())
345 ModifiedRegs.setBitsNotInMask(MO.getRegMask());
347 if (!MO.isReg())
349 unsigned Reg = MO.getReg();
350 if (MO.isDef()) {
354 assert(MO.isUse() && "Reg operand not a def and not a use?!?");
H A DAArch64InstrInfo.cpp673 MachineOperand &MO = Instr->getOperand(OpIdx); local
682 if (MO.isFI())
685 assert(MO.isReg() &&
688 unsigned Reg = MO.getReg();
826 const MachineOperand &MO = Instr.getOperand(IO); local
827 if (MO.isRegMask() && MO.clobbersPhysReg(AArch64::NZCV)) {
831 if (!MO.isReg() || MO.getReg() != AArch64::NZCV)
833 if (MO
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/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
216 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument
219 if (MO.isReg())
220 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
222 assert(MO.isImm() && "did not expect relocated expression");
223 return static_cast<unsigned>(MO.getImm());
230 const MCOperand &MO = MI.getOperand(OpIdx); local
233 if (MO.isImm())
234 ImmVal = static_cast<uint32_t>(MO.getImm());
236 assert(MO
251 const MCOperand &MO = MI.getOperand(OpIdx); local
278 const MCOperand &MO = MI.getOperand(OpIdx); local
304 const MCOperand &MO = MI.getOperand(OpIdx); local
326 const MCOperand &MO = MI.getOperand(OpIdx); local
355 const MCOperand &MO = MI.getOperand(OpIdx); local
374 const MCOperand &MO = MI.getOperand(OpIdx); local
396 const MCOperand &MO = MI.getOperand(OpIdx); local
424 const MCOperand &MO = MI.getOperand(OpIdx); local
448 const MCOperand &MO = MI.getOperand(OpIdx); local
456 const MCOperand &MO = MI.getOperand(OpIdx); local
465 const MCOperand &MO = MI.getOperand(OpIdx); local
474 const MCOperand &MO = MI.getOperand(OpIdx); local
484 const MCOperand &MO = MI.getOperand(OpIdx); local
493 const MCOperand &MO = MI.getOperand(OpIdx); local
502 const MCOperand &MO = MI.getOperand(OpIdx); local
511 const MCOperand &MO = MI.getOperand(OpIdx); local
520 const MCOperand &MO = MI.getOperand(OpIdx); local
529 const MCOperand &MO = MI.getOperand(OpIdx); local
538 const MCOperand &MO = MI.getOperand(OpIdx); local
547 const MCOperand &MO = MI.getOperand(OpIdx); local
556 const MCOperand &MO = MI.getOperand(OpIdx); local
566 const MCOperand &MO = MI.getOperand(OpIdx); local
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/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp98 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 bool A15SDOptimizer::usesRegClass(MachineOperand &MO, argument
135 if (!MO.isReg())
137 unsigned Reg = MO.getReg();
160 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
162 assert(MO->isReg() && "Non-register operand found!");
163 if (!MO) return ARM::ssub_0;
171 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
193 MachineOperand &MO = MI->getOperand(i); local
194 if ((!MO
409 MachineOperand &MO = MI->getOperand(i); local
[all...]
H A DThumb2SizeReduction.cpp259 for (const MachineOperand &MO : CPSRDef->operands()) {
260 if (!MO.isReg() || MO.isUndef() || MO.isUse())
262 unsigned Reg = MO.getReg();
268 for (const MachineOperand &MO : Use->operands()) {
269 if (!MO.isReg() || MO.isUndef() || MO.isDef())
271 unsigned Reg = MO
341 const MachineOperand &MO = MI->getOperand(i); local
766 const MachineOperand &MO = MI->getOperand(i); local
837 const MachineOperand &MO = MI->getOperand(i); local
975 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR); local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp571 MachineOperand &MO = MI->getOperand(i); local
572 if (MO.isReg() && MO.isUse()) {
573 unsigned feederReg = MO.getReg();
584 MO.setIsKill();
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp343 MachineOperand &MO = II->getOperand(i); local
344 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
345 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
346 Candidates.reset(MO.getReg());
360 MachineOperand &MO = II->getOperand(i); local
361 if (MO.isReg() && MO.isDef()) {
362 DefReg = MO
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/external/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp142 const MachineOperand &MO = MI->getOperand(I); local
143 if (MO.isReg()) {
144 if (unsigned MOReg = MO.getReg()) {
146 if (MO.isUse()) {
150 if (MO.isDef()) {
/external/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp73 static void printSymbolOperand(X86AsmPrinter &P, const MachineOperand &MO, argument
75 switch (MO.getType()) {
78 O << *P.GetCPISymbol(MO.getIndex());
79 P.printOffset(MO.getOffset(), O);
82 const GlobalValue *GV = MO.getGlobal();
85 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB)
87 else if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
88 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
89 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
95 if (MO
183 const MachineOperand &MO = MI->getOperand(OpNo); local
202 const MachineOperand &MO = MI->getOperand(OpNo); local
348 printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO, char Mode, raw_ostream &O) argument
386 const MachineOperand &MO = MI->getOperand(OpNo); local
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp406 MachineOperand &MO = Cond[1]; local
407 switch (MO.getImm()) {
409 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
412 MO.setImm(OPCODE_IS_ZERO_INT);
415 MO.setImm(OPCODE_IS_NOT_ZERO);
418 MO.setImm(OPCODE_IS_ZERO);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
236 const MCOperand &MO = MI.getOperand(OpIdx); local
245 if (MO.isReg()) {
246 unsigned reg = MO.getReg();
264 if (MO.isReg()) {
265 EmitByte(getHWRegChan(MO.getReg()), OS);
273 (MO.isReg() &&
274 (MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
300 const MCOperand &MO local
620 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixup) const argument
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