Searched defs:RC (Results 76 - 100 of 138) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp215 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument
220 switch (RC->getID()) {
246 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)const {
251 if (RC == &PPC::F8RCRegClass)
253 else if (RC == &PPC::VRRCRegClass)
257 return TargetRegisterInfo::getLargestLegalSuperClass(RC);
799 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; local
800 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
801 SReg = MF.getRegInfo().createVirtualRegister(RC);
H A DPPCFrameLowering.cpp1340 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; local
1341 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1342 RC->getAlignment(),
1351 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1352 RC->getAlignment(),
1417 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
1419 CSI[i].getFrameIdx(), RC, TRI);
1564 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
1566 RC, TRI);
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
433 TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
460 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
461 TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
568 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
575 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
576 RC->getAlignment(),
579 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
580 RC->getAlignment(),
/external/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp33 const CodeGenRegisterClass &RC = *RCs[rc]; local
34 if (!RC.contains(Reg))
39 VT = RC.getValueTypeNum(0);
44 assert(VT == RC.getValueTypeNum(0));
H A DRegisterInfoEmitter.cpp167 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; local
171 const CodeGenRegister::Set &Regs = RC.getMembers();
176 RC.buildRegUnitSet(RegUnits);
180 OS << "}, \t// " << RC.getName() << "\n";
183 << " return RCWeightTable[RC->getID()];\n"
285 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
291 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
853 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
854 ArrayRef<Record*> Order = RC
887 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
995 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local
1033 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
1098 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
1127 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
1143 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local
1179 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local
1245 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; local
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H A DCodeGenRegisters.h265 // R:SubRegIndex in this RC for all R in SuperRC.
302 // Returns true if RC is a subclass.
303 // RC is a sub-class of this class if it is a valid replacement for any
307 // 1. All RC registers are also in this.
308 // 2. The RC spill size must not be smaller than our spill size.
309 // 3. RC spill alignment must be compatible with ours.
311 bool hasSubClass(const CodeGenRegisterClass *RC) const {
312 return SubClasses.test(RC->EnumValue);
381 Key(const CodeGenRegisterClass &RC) argument
382 : Members(&RC
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/external/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h562 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
565 /// register to be a common subclass of RC and the current register class,
572 const TargetRegisterClass *RC,
980 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); local
981 PSet = TRI->getRegClassPressureSets(RC);
982 Weight = TRI->getRegClassWeight(RC).RegWeight;
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h199 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
529 const TargetRegisterClass *RC,
542 const TargetRegisterClass *RC,
736 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
526 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
539 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DTargetLowering.h315 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; local
316 assert(RC && "This value type is not natively supported!");
317 return RC;
328 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; local
329 return RC;
1074 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { argument
1076 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1077 RegClassForVT[VT.SimpleTy] = RC;
1847 bool isLegalRC(const TargetRegisterClass *RC) const;
/external/llvm/lib/CodeGen/
H A DMachineBasicBlock.cpp352 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { argument
355 assert(RC && "Register class is required");
369 if (!MRI.constrainRegClass(VirtReg, RC))
375 unsigned VirtReg = MRI.createVirtualRegister(RC);
H A DMachineFunction.cpp436 const TargetRegisterClass *RC) {
446 // physical register and is a sub class of the specified RC.
447 assert((VRegRC == RC || (VRegRC->contains(PReg) &&
448 RC->hasSubClassEq(VRegRC))) &&
452 VReg = MRI.createVirtualRegister(RC);
435 addLiveIn(unsigned PReg, const TargetRegisterClass *RC) argument
H A DMachineLICM.cpp786 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
787 MVT VT = *RC->vt_begin();
789 RCId = RC->getID();
1263 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); local
1265 unsigned Reg = MRI->createVirtualRegister(RC);
H A DTwoAddressInstructionPass.cpp1193 const TargetRegisterClass *RC = local
1196 unsigned Reg = MRI->createVirtualRegister(RC);
1320 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1322 MRI->constrainRegClass(DstReg, RC);
1391 const TargetRegisterClass *RC = MRI->getRegClass(RegB); local
1394 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1398 RC = nullptr;
1437 MRI->constrainRegClass(RegA, RC);
H A DMachineInstr.cpp1601 OS << ":RC" << RCID;
1648 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); local
1649 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1651 if (MRI->getRegClass(VirtRegs[j]) != RC) {
H A DMachineVerifier.cpp913 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
916 TRI->getSubClassWithSubReg(RC, SubIdx);
919 *OS << "Register class " << RC->getName()
923 if (RC != SRC) {
925 *OS << "Register class " << RC->getName()
934 TRI->getLargestLegalSuperClass(RC);
945 if (!RC->hasSuperClassEq(DRC)) {
948 << RC->getName() << " register\n";
H A DRegAllocGreedy.cpp816 // Check of any registers in RC are below CostPerUseLimit.
817 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg); local
818 unsigned MinCost = RegClassInfo.getMinCost(RC);
820 DEBUG(dbgs() << RC->getName() << " minimum cost = " << MinCost
828 OrderLimit = RegClassInfo.getLastCostChange(RC);
/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp312 unsigned RC; local
313 InlineAsm::hasRegClassConstraint(Flags, RC);
314 if (RC == ARM::GPRPairRegClassID) {
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1205 const TargetRegisterClass * RC; local
1210 RC = &MSP430::GR8RegClass;
1214 RC = &MSP430::GR16RegClass;
1218 RC = &MSP430::GR8RegClass;
1222 RC = &MSP430::GR16RegClass;
1226 RC = &MSP430::GR8RegClass;
1230 RC = &MSP430::GR16RegClass;
1259 unsigned ShiftReg = RI.createVirtualRegister(RC);
1260 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
/external/llvm/lib/Target/R600/
H A DAMDGPUISelDAGToDAG.cpp247 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo()); local
248 if (!RC) {
251 if (SIRI->isSGPRClass(RC)) {
337 SDValue RC, SubReg0, SubReg1; local
342 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
346 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
352 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp593 const TargetRegisterClass *RC,
600 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
609 const TargetRegisterClass *RC,
616 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
1088 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, argument
1091 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1094 } else if (RC == &SystemZ::GRH32BitRegClass) {
1097 } else if (RC == &SystemZ::GRX32BitRegClass) {
1100 } else if (RC
589 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
606 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/chromium_org/third_party/webrtc/modules/audio_coding/codecs/isac/main/source/
H A Dentropy_coding.c523 /* Find RC coefficients. */
526 /* Quantize & code RC Coefficient. */
529 /* RC -> AR coefficients */
595 void WebRtcIsac_Rc2Poly(double* RC, int N, double* a) { argument
604 a[m] = RC[m - 1];
606 a[k] += RC[m - 1] * tmp[m - k];
613 void WebRtcIsac_Poly2Rc(double* a, int N, double* RC) { argument
618 RC[N - 1] = a[N];
620 tmp_inv = 1.0 / (1.0 - RC[m] * RC[
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/external/chromium_org/third_party/webrtc/modules/rtp_rtcp/source/
H A Drtcp_sender.cc799 // hdr |V=2|P| RC | PT=IJ=195 | length |
810 // (inside a compound RTCP packet), and MUST have the same value for RC
833 uint8_t RC = 1; local
834 rtcpbuffer[pos++]=(uint8_t)0x80 + RC;
/external/llvm/lib/Analysis/
H A DScalarEvolution.cpp538 const SCEVConstant *RC = cast<SCEVConstant>(RHS); local
542 const APInt &RA = RC->getValue()->getValue();
582 const SCEVNAryExpr *RC = cast<SCEVNAryExpr>(RHS); local
585 unsigned LNumOps = LC->getNumOperands(), RNumOps = RC->getNumOperands();
592 long X = compare(LC->getOperand(i), RC->getOperand(i));
601 const SCEVUDivExpr *RC = cast<SCEVUDivExpr>(RHS); local
604 long X = compare(LC->getLHS(), RC->getLHS());
607 return compare(LC->getRHS(), RC->getRHS());
614 const SCEVCastExpr *RC = cast<SCEVCastExpr>(RHS); local
617 return compare(LC->getOperand(), RC
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1322 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { argument
1323 return MRI.createVirtualRegister(RC);
1344 const TargetRegisterClass* RC) {
1345 unsigned ResultReg = createResultReg(RC);
1353 const TargetRegisterClass *RC,
1357 unsigned ResultReg = createResultReg(RC);
1374 const TargetRegisterClass *RC,
1379 unsigned ResultReg = createResultReg(RC);
1398 const TargetRegisterClass *RC,
1404 unsigned ResultReg = createResultReg(RC);
1343 FastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass* RC) argument
1352 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
1373 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
1397 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
1425 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
1449 FastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument
1474 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument
1497 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
1524 FastEmitInst_rrii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm1, uint64_t Imm2) argument
1551 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
1567 FastEmitInst_ii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm1, uint64_t Imm2) argument
1590 const TargetRegisterClass *RC = MRI.getRegClass(Op0); local
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H A DScheduleDAGRRList.cpp292 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); local
293 RegClass = RC->getID();
301 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); local
302 RegClass = RC->getID();
309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); local
310 RegClass = RC->getID();
1443 const TargetRegisterClass *RC = local
1445 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
1447 // If cross copy register class is the same as RC, then it must be possible
1449 // If cross copy register class is not the same as RC, the
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