/external/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.cpp | 211 bool R600SchedStrategy::regBelongsToClass(unsigned Reg, argument 213 if (!TargetRegisterInfo::isVirtualRegister(Reg)) { 214 return RC->contains(Reg); 216 return MRI->getRegClass(Reg) == RC;
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H A D | R600OptimizeVectorRegisters.cpp | 49 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { argument 50 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), 54 if (MRI.isReserved(Reg)) { 57 llvm_unreachable("Reg without a def"); 89 bool areAllUsesSwizzeable(unsigned Reg) const; 180 unsigned Reg = RSI->Instr->getOperand(0).getReg(); local 212 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg) 217 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), 264 bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const { 265 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), 331 unsigned Reg = MI->getOperand(1).getReg(); local 345 unsigned Reg = MI->getOperand(0).getReg(); local [all...] |
H A D | SIInsertWaits.cpp | 142 unsigned Reg = Op.getReg(); local 143 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); 192 unsigned Reg = Op.getReg(); local 193 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); 198 Result.first = TRI->getEncodingValue(Reg);
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H A D | SILowerControlFlow.cpp | 182 unsigned Reg = MI.getOperand(0).getReg(); local 185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) 188 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) 190 .addReg(Reg); 279 unsigned Reg = MI.getOperand(0).getReg(); local 284 .addReg(Reg);
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/external/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 80 unsigned Reg); 258 unsigned Reg = MO.getReg(); local 261 // check whether Reg is defined or used before delay slot. 262 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg)) 266 // check whether Reg is defined before delay slot. 267 if (IsRegInSet(RegDefs, Reg)) 288 const MachineOperand &Reg = MI->getOperand(0); local 289 assert(Reg.isReg() && "CALL first operand is not a register."); 290 assert(Reg 313 unsigned Reg = MO.getReg(); local 329 IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) argument [all...] |
/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); local 40 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); 48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); local 49 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 54 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset; 97 unsigned Reg = CSRegs[I]; local 98 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) { 140 unsigned Reg = CSI[I].getReg(); local 141 if (SystemZ::GR64BitRegClass.contains(Reg)) { 142 unsigned Offset = RegSpillOffsets[Reg]; 145 LowGPR = Reg; 161 unsigned Reg = SystemZ::ArgGPRs[FirstGPR]; local 162 unsigned Offset = RegSpillOffsets[Reg]; 186 unsigned Reg = CSI[I].getReg(); local 199 unsigned Reg = CSI[I].getReg(); local 226 unsigned Reg = CSI[I].getReg(); local 256 unsigned Reg = CSI[I].getReg(); local 282 emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, unsigned Reg, int64_t NumBytes, const TargetInstrInfo *TII) argument 335 unsigned Reg = Save.getReg(); local 382 unsigned Reg = Save.getReg(); local [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 35 bool IsStackReg(unsigned Reg) { argument 36 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
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/external/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 183 unsigned Reg = MO.getReg(); local 184 if (X86II::isX86_64NonExtLowByteReg(Reg))
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H A D | X86InstrBuilder.h | 44 unsigned Reg; member in union:llvm::X86AddressMode::__anon26195 57 Base.Reg = 0; 65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, 91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument 93 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction. 94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); 104 /// [Reg + Offset], i.e., one with no scale or index, but with a 109 unsigned Reg, bool isKill, int Offset) { 110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 114 /// [Reg 108 addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) argument [all...] |
H A D | X86MachineFunctionInfo.h | 118 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument 121 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
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H A D | X86RegisterInfo.cpp | 458 unsigned Reg, int &FrameIdx) const { 461 if (Reg == FramePtr && TFI->hasFP(MF)) { 534 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT, argument 540 switch (Reg) { 541 default: return getX86SubSuperRegister(Reg, MVT::i64); 560 switch (Reg) { 597 switch (Reg) { 633 switch (Reg) { 669 switch (Reg) { 707 unsigned get512BitSuperRegister(unsigned Reg) { argument 457 hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const argument [all...] |
H A D | X86VZeroUpper.cpp | 104 static bool isYmmReg(unsigned Reg) { argument 105 return (Reg >= X86::YMM0 && Reg <= X86::YMM15);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 115 SDValue Reg; local 122 Reg = CurDAG->getRegister(XCore::CP, MVT::i32); 125 Reg = CurDAG->getRegister(XCore::DP, MVT::i32); 129 OutOps.push_back(Reg);
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H A D | XCoreInstrInfo.cpp | 443 unsigned Reg, uint64_t Value) const { 449 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N); 453 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value); 459 return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg) 440 loadImmediate( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const argument
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H A D | XCoreRegisterInfo.cpp | 63 unsigned Reg, unsigned FrameReg, int Offset ) { 70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) 94 unsigned Reg, unsigned FrameReg, 106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) 113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) 130 unsigned Reg, int Offset) { 140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 61 InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset ) argument 92 InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS ) argument 128 InsertSPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset) argument 161 InsertSPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset, RegScavenger *RS ) argument 305 unsigned Reg = MI.getOperand(0).getReg(); local [all...] |
/external/llvm/tools/llvm-objdump/ |
H A D | COFFDump.cpp | 50 static StringRef getUnwindRegisterName(uint8_t Reg) { argument 51 switch(Reg) {
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/external/llvm/utils/TableGen/ |
H A D | PseudoLoweringEmitter.cpp | 28 enum MapKind { Operand, Imm, Reg }; enumerator in enum:__anon26603::PseudoLoweringEmitter::OpData::MapKind 33 Record *Reg; // Physical register. member in union:__anon26603::PseudoLoweringEmitter::OpData::__anon26604 83 OperandMap[BaseIdx + i].Kind = OpData::Reg; 84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); 238 case OpData::Reg: { 239 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; local 242 if (Reg->getName() == "zero_reg") 245 o << Reg->getValueAsString("Namespace") << "::" 246 << Reg [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 315 unsigned Reg, EVT VT) const { 319 if (!MRI.isLiveIn(Reg)) { 321 MRI.addLiveIn(Reg, VirtualRegister); 323 VirtualRegister = MRI.getLiveInVirtReg(Reg); 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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H A D | AMDGPUInstrInfo.cpp | 165 unsigned Reg, bool UnfoldLoad, 164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
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H A D | R600ISelLowering.cpp | 262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local 263 if (!MRI.isLiveOut(Reg)) { 264 MRI.addLiveOut(Reg); 266 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2)); 283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local 284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
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H A D | SIISelLowering.cpp | 367 unsigned Reg = dstClass->getRegister(SGPRIndex); local 369 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 349 unsigned Reg = MI->getOperand(idx).getReg(); local 350 switch (Reg) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | LiveInterval.h | 535 LiveInterval(unsigned Reg, float Weight) argument 536 : reg(Reg), weight(Weight) {}
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H A D | MachineTraceMetrics.h | 121 unsigned Reg; member in struct:llvm::MachineTraceMetrics::LiveInReg 127 LiveInReg(unsigned Reg, unsigned Height = 0) : Reg(Reg), Height(Height) {} argument
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