Searched refs:MRI (Results 76 - 100 of 247) sorted by relevance

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/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp212 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { argument
215 unsigned SEH = MRI->getEncodingValue(Reg);
216 MRI->mapLLVMRegToSEHReg(Reg, SEH);
260 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument
289 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
295 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
376 const MCRegisterInfo &MRI,
379 return new X86ATTInstPrinter(MAI, MII, MRI);
381 return new X86IntelInstPrinter(MAI, MII, MRI);
372 createX86MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp60 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, argument
73 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
116 const MCRegisterInfo &MRI,
119 return new AArch64InstPrinter(MAI, MII, MRI, STI);
121 return new AArch64AppleInstPrinter(MAI, MII, MRI, STI);
112 createAArch64MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/CodeGen/
H A DMachineLICM.cpp69 MachineRegisterInfo *MRI; member in class:__anon25767::MachineLICM
332 MRI = &MF.getRegInfo();
335 PreRegAlloc = MRI->isSSA();
776 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) { argument
777 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
786 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
831 bool isKill = isOperandKill(MO, MRI);
860 else if (!isNew && isOperandKill(MO, MRI)) {
941 if (!MRI->isConstantPhysReg(Reg, *I.getParent()->getParent()))
958 assert(MRI
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H A DCalcSpillWeights.cpp33 MachineRegisterInfo &MRI = MF.getRegInfo(); local
35 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
37 if (MRI.reg_nodbg_empty(Reg))
H A DMachineCopyPropagation.cpp38 MachineRegisterInfo *MRI; member in class:__anon25763::MachineCopyPropagation
162 if (!MRI->isReserved(Def) &&
163 (!MRI->isReserved(Src) || NoInterveningSideEffect(CopyMI, MI)) &&
282 if (MRI->isReserved(Reg) || !MaskMO.clobbersPhysReg(Reg))
321 if (!MRI->isReserved((*DI)->getOperand(0).getReg())) {
340 MRI = &MF.getRegInfo();
H A DPHIElimination.cpp51 MachineRegisterInfo *MRI; // Machine register information member in class:__anon25782::PHIElimination
128 MRI = &MF.getRegInfo();
135 MRI->leaveSSA();
157 if (MRI->use_nodbg_empty(DefReg)) {
201 const MachineRegisterInfo *MRI) {
202 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
211 const MachineRegisterInfo *MRI) {
213 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
244 if (isSourceDefinedByImplicitDef(MPhi, MRI))
361 isImplicitlyDefined(SrcReg, MRI);
200 isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo *MRI) argument
210 isSourceDefinedByImplicitDef(const MachineInstr *MPhi, const MachineRegisterInfo *MRI) argument
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H A DMachineInstr.cpp57 MachineRegisterInfo &MRI = MF->getRegInfo(); local
58 MRI.removeRegOperandFromUseList(this);
60 MRI.addRegOperandToUseList(this);
95 // MRI may keep uses and defs in different list positions.
99 MachineRegisterInfo &MRI = MF->getRegInfo(); local
100 MRI.removeRegOperandFromUseList(this);
102 MRI.addRegOperandToUseList(this);
595 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { argument
598 MRI.removeRegOperandFromUseList(&Operands[i]);
604 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { argument
620 moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI) argument
677 MachineRegisterInfo *MRI = getRegInfo(); local
1463 const MachineRegisterInfo *MRI = nullptr; local
1545 const MachineRegisterInfo &MRI = MF->getRegInfo(); local
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp241 MachineRegisterInfo &MRI = MF.getRegInfo(); local
249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
254 MRI.setRegClass(MO.getReg(), newRegClass);
H A DSIISelLowering.cpp69 MachineRegisterInfo & MRI = BB->getParent()->getRegInfo(); local
127 LowerSI_INTERP(MI, *BB, I, MRI);
130 LowerSI_INTERP_CONST(MI, *BB, I, MRI);
133 LowerSI_KIL(MI, *BB, I, MRI);
136 LowerSI_V_CNDLT(MI, *BB, I, MRI);
150 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
152 unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
183 MachineRegisterInfo &MRI) const
189 unsigned M0 = MRI
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H A DR600ISelLowering.cpp57 MachineRegisterInfo &MRI = MF->getRegInfo(); local
111 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
120 unsigned NewAddr = MRI.createVirtualRegister(
122 unsigned ShiftValue = MRI.createVirtualRegister(
157 unsigned t0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
158 unsigned t1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
179 unsigned t0 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
180 unsigned t1 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
260 MachineRegisterInfo &MRI = MF.getRegInfo(); local
263 if (!MRI
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/external/llvm/include/llvm/CodeGen/
H A DLiveVariables.h111 MachineRegisterInfo &MRI);
130 MachineRegisterInfo* MRI; member in class:llvm::LiveVariables
282 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
H A DRegisterScavenging.h34 MachineRegisterInfo* MRI; member in class:llvm::RegScavenger
165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
H A DVirtRegMap.h41 MachineRegisterInfo *MRI; member in class:llvm::VirtRegMap
85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
H A DLiveRegMatrix.h41 MachineRegisterInfo *MRI; member in class:llvm::LiveRegMatrix
/external/llvm/lib/MC/MCAnalysis/
H A DMCModuleYAML.cpp34 // 1- Generate an MII/MRI method using a tablegen StringMatcher
35 // 2- Write an MII/MRI method using std::lower_bound and the assumption that
45 // can be made against having {MII,MRI}::getName).
48 // the Right Thing (tm) and move the functionality to MII/MRI.
57 const MCRegisterInfo &MRI; member in class:llvm::__anon25873::InstrRegInfoHolder
58 InstrRegInfoHolder(const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
60 RegEnumValueByName(NextPowerOf2(MRI.getNumRegs())), MII(MII), MRI(MRI) {
63 for (int i = 0, e = MRI
439 mcmodule2yaml(raw_ostream &OS, const MCModule &MCM, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
448 yaml2mcmodule(std::unique_ptr<MCModule> &MCM, StringRef YamlContent, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/external/llvm/lib/Target/XCore/MCTargetDesc/
H A DXCoreMCTargetDesc.cpp56 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, argument
88 const MCRegisterInfo &MRI,
90 return new XCoreInstPrinter(MAI, MII, MRI);
84 createXCoreMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp241 MachineRegisterInfo &MRI = MF.getRegInfo(); local
249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
254 MRI.setRegClass(MO.getReg(), newRegClass);
H A DSIISelLowering.cpp69 MachineRegisterInfo & MRI = BB->getParent()->getRegInfo(); local
127 LowerSI_INTERP(MI, *BB, I, MRI);
130 LowerSI_INTERP_CONST(MI, *BB, I, MRI);
133 LowerSI_KIL(MI, *BB, I, MRI);
136 LowerSI_V_CNDLT(MI, *BB, I, MRI);
150 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
152 unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
183 MachineRegisterInfo &MRI) const
189 unsigned M0 = MRI
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H A DR600ISelLowering.cpp57 MachineRegisterInfo &MRI = MF->getRegInfo(); local
111 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
120 unsigned NewAddr = MRI.createVirtualRegister(
122 unsigned ShiftValue = MRI.createVirtualRegister(
157 unsigned t0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
158 unsigned t1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
179 unsigned t0 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
180 unsigned t1 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
260 MachineRegisterInfo &MRI = MF.getRegInfo(); local
263 if (!MRI
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/external/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp32 const MachineRegisterInfo *MRI; member in class:__anon25948::AArch64StorePairSuppress
123 MRI = &MF->getRegInfo();
/external/llvm/lib/Target/Hexagon/InstPrinter/
H A DHexagonInstPrinter.h27 const MCRegisterInfo &MRI)
28 : MCInstPrinter(MAI, MII, MRI), MII(MII) {}
25 HexagonInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp69 MachineRegisterInfo &MRI; member in class:__anon26056::ExpandPseudo
74 : MF(MF_), MRI(MF.getRegInfo()) {}
135 unsigned VR = MRI.createVirtualRegister(RC);
155 unsigned VR = MRI.createVirtualRegister(RC);
178 unsigned VR0 = MRI.createVirtualRegister(RC);
179 unsigned VR1 = MRI.createVirtualRegister(RC);
208 unsigned VR0 = MRI.createVirtualRegister(RC);
209 unsigned VR1 = MRI.createVirtualRegister(RC);
245 unsigned VR0 = MRI.createVirtualRegister(RC);
246 unsigned VR1 = MRI
299 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local
514 MachineRegisterInfo &MRI = MF.getRegInfo(); local
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/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.h25 const MCRegisterInfo &MRI)
26 : MCInstPrinter(MAI, MII, MRI) {}
24 AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp161 DstRC = MRI->getRegClass(VRBase);
175 VRBase = MRI->createVirtualRegister(DstRC);
250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
264 VRBase = MRI->createVirtualRegister(RC);
290 VReg = MRI->createVirtualRegister(RC);
332 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
333 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
438 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
444 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
454 unsigned NewReg = MRI
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/external/chromium_org/v8/src/compiler/ia32/
H A Dinstruction-codes-ia32.h69 // MRI = [register + immediate]
74 V(MRI) /* [%r0 + K] */ \

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