Searched refs:hw (Results 76 - 100 of 198) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_tex.c276 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) {
278 rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor;
302 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) {
304 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK;
305 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK);
370 rmesa->hw.tex[i].dirty = GL_FALSE;
371 rmesa->hw.cube[i].dirty = GL_FALSE;
H A Dradeon_texstate.c595 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine ||
596 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) {
598 rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine;
599 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine;
746 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) |
754 if (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) {
755 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
760 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE;
786 uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
787 GLuint se_coord_fmt = rmesa->hw
[all...]
H A Dradeon_context.c101 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
104 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
122 rmesa->hw.zbs.dirty = 1;
123 radeon->hw.is_dirty = 1;
252 rmesa->radeon.hw.all_dirty = GL_TRUE;
H A Dradeon_common.c283 /* need to re-compute stencil hw state */
476 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) {
477 if (!radeon->hw.is_dirty)
479 foreach(atom, &radeon->hw.atomlist) {
489 foreach(atom, &radeon->hw.atomlist) {
536 if (radeon->hw.all_dirty || emitAll) {
537 foreach(atom, &radeon->hw.atomlist)
540 foreach(atom, &radeon->hw.atomlist) {
568 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw
[all...]
/external/wpa_supplicant_8/hostapd/src/ap/
H A Dhw_features.c732 u16 hw = iface->current_mode->ht_capab; local
736 !(hw & HT_CAP_INFO_LDPC_CODING_CAP)) {
743 !(hw & HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET)) {
749 if ((conf & HT_CAP_INFO_SMPS_MASK) != (hw & HT_CAP_INFO_SMPS_MASK) &&
757 !(hw & HT_CAP_INFO_GREEN_FIELD)) {
764 !(hw & HT_CAP_INFO_SHORT_GI20MHZ)) {
771 !(hw & HT_CAP_INFO_SHORT_GI40MHZ)) {
777 if ((conf & HT_CAP_INFO_TX_STBC) && !(hw & HT_CAP_INFO_TX_STBC)) {
784 (hw & HT_CAP_INFO_RX_STBC_MASK)) {
791 !(hw
824 ieee80211ac_cap_check(u32 hw, u32 conf, u32 cap, const char *name) argument
842 ieee80211ac_cap_check_max(u32 hw, u32 conf, u32 cap, const char *name) argument
860 u32 hw = iface->current_mode->vht_capab; local
[all...]
/external/wpa_supplicant_8/src/ap/
H A Dhw_features.c732 u16 hw = iface->current_mode->ht_capab; local
736 !(hw & HT_CAP_INFO_LDPC_CODING_CAP)) {
743 !(hw & HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET)) {
749 if ((conf & HT_CAP_INFO_SMPS_MASK) != (hw & HT_CAP_INFO_SMPS_MASK) &&
757 !(hw & HT_CAP_INFO_GREEN_FIELD)) {
764 !(hw & HT_CAP_INFO_SHORT_GI20MHZ)) {
771 !(hw & HT_CAP_INFO_SHORT_GI40MHZ)) {
777 if ((conf & HT_CAP_INFO_TX_STBC) && !(hw & HT_CAP_INFO_TX_STBC)) {
784 (hw & HT_CAP_INFO_RX_STBC_MASK)) {
791 !(hw
824 ieee80211ac_cap_check(u32 hw, u32 conf, u32 cap, const char *name) argument
842 ieee80211ac_cap_check_max(u32 hw, u32 conf, u32 cap, const char *name) argument
860 u32 hw = iface->current_mode->vht_capab; local
[all...]
/external/wpa_supplicant_8/wpa_supplicant/src/ap/
H A Dhw_features.c732 u16 hw = iface->current_mode->ht_capab; local
736 !(hw & HT_CAP_INFO_LDPC_CODING_CAP)) {
743 !(hw & HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET)) {
749 if ((conf & HT_CAP_INFO_SMPS_MASK) != (hw & HT_CAP_INFO_SMPS_MASK) &&
757 !(hw & HT_CAP_INFO_GREEN_FIELD)) {
764 !(hw & HT_CAP_INFO_SHORT_GI20MHZ)) {
771 !(hw & HT_CAP_INFO_SHORT_GI40MHZ)) {
777 if ((conf & HT_CAP_INFO_TX_STBC) && !(hw & HT_CAP_INFO_TX_STBC)) {
784 (hw & HT_CAP_INFO_RX_STBC_MASK)) {
791 !(hw
824 ieee80211ac_cap_check(u32 hw, u32 conf, u32 cap, const char *name) argument
842 ieee80211ac_cap_check_max(u32 hw, u32 conf, u32 cap, const char *name) argument
860 u32 hw = iface->current_mode->vht_capab; local
[all...]
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
H A Dr200_vertprog.c106 GLfloat *fcmd = (GLfloat *)&rmesa->hw.vpp[0].cmd[VPP_CMD_0 + 1];
139 fcmd = (GLfloat *)&rmesa->hw.vpp[1].cmd[VPP_CMD_0 + 1];
143 rmesa->hw.vpp[0].cmd_size =
145 tmp.i = rmesa->hw.vpp[0].cmd[VPP_CMD_0];
147 rmesa->hw.vpp[0].cmd[VPP_CMD_0] = tmp.i;
149 rmesa->hw.vpp[1].cmd_size = 1 + 4 * (paramList->NumParameters - 96);
150 tmp.i = rmesa->hw.vpp[1].cmd[VPP_CMD_0];
152 rmesa->hw.vpp[1].cmd[VPP_CMD_0] = tmp.i;
451 /* Initial value should be last tmp reg that hw supports.
491 and 13 in a hw verte
[all...]
H A Dr200_tex.c318 if ( rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] != envColor ) {
320 rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] = envColor;
342 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] & R200_LOD_BIAS_MASK) != b ) {
344 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] &= ~R200_LOD_BIAS_MASK;
345 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] |= b;
353 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_GEN_TEX_0 << unit;
355 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~(R200_PS_GEN_TEX_0 << unit);
428 rmesa->hw.tex[i].dirty = GL_FALSE;
429 rmesa->hw.cube[i].dirty = GL_FALSE;
H A Dradeon_common.c283 /* need to re-compute stencil hw state */
476 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) {
477 if (!radeon->hw.is_dirty)
479 foreach(atom, &radeon->hw.atomlist) {
489 foreach(atom, &radeon->hw.atomlist) {
536 if (radeon->hw.all_dirty || emitAll) {
537 foreach(atom, &radeon->hw.atomlist)
540 foreach(atom, &radeon->hw.atomlist) {
568 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw
[all...]
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_vertprog.c106 GLfloat *fcmd = (GLfloat *)&rmesa->hw.vpp[0].cmd[VPP_CMD_0 + 1];
139 fcmd = (GLfloat *)&rmesa->hw.vpp[1].cmd[VPP_CMD_0 + 1];
143 rmesa->hw.vpp[0].cmd_size =
145 tmp.i = rmesa->hw.vpp[0].cmd[VPP_CMD_0];
147 rmesa->hw.vpp[0].cmd[VPP_CMD_0] = tmp.i;
149 rmesa->hw.vpp[1].cmd_size = 1 + 4 * (paramList->NumParameters - 96);
150 tmp.i = rmesa->hw.vpp[1].cmd[VPP_CMD_0];
152 rmesa->hw.vpp[1].cmd[VPP_CMD_0] = tmp.i;
451 /* Initial value should be last tmp reg that hw supports.
491 and 13 in a hw verte
[all...]
H A Dr200_tex.c318 if ( rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] != envColor ) {
320 rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] = envColor;
342 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] & R200_LOD_BIAS_MASK) != b ) {
344 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] &= ~R200_LOD_BIAS_MASK;
345 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] |= b;
353 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_GEN_TEX_0 << unit;
355 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~(R200_PS_GEN_TEX_0 << unit);
428 rmesa->hw.tex[i].dirty = GL_FALSE;
429 rmesa->hw.cube[i].dirty = GL_FALSE;
H A Dradeon_common.c283 /* need to re-compute stencil hw state */
476 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) {
477 if (!radeon->hw.is_dirty)
479 foreach(atom, &radeon->hw.atomlist) {
489 foreach(atom, &radeon->hw.atomlist) {
536 if (radeon->hw.all_dirty || emitAll) {
537 foreach(atom, &radeon->hw.atomlist)
540 foreach(atom, &radeon->hw.atomlist) {
568 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw
[all...]
/external/dhcpcd/
H A Dbpf.c142 struct ether_header hw; local
145 memset(&hw, 0, ETHER_HDR_LEN);
146 memset(&hw.ether_dhost, 0xff, ETHER_ADDR_LEN);
147 hw.ether_type = htons(protocol);
148 iov[0].iov_base = &hw;
/external/chromium_org/third_party/libjingle/source/talk/media/webrtc/
H A Dwebrtcvoe.h108 webrtc::VoEHardware* hw,
121 hw_(hw),
136 webrtc::VoEHardware* hw() const { return hw_.get(); } function in class:cricket::VoEWrapper
103 VoEWrapper(webrtc::VoEAudioProcessing* processing, webrtc::VoEBase* base, webrtc::VoECodec* codec, webrtc::VoEDtmf* dtmf, webrtc::VoEFile* file, webrtc::VoEHardware* hw, webrtc::VoEExternalMedia* media, webrtc::VoENetEqStats* neteq, webrtc::VoENetwork* network, webrtc::VoERTP_RTCP* rtp, webrtc::VoEVideoSync* sync, webrtc::VoEVolumeControl* volume) argument
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/svga/
H A Dsvga_pipe_misc.c54 struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer; local
59 pipe_surface_reference(&hw->cbufs[i], NULL);
63 pipe_surface_reference(&hw->zsbuf, NULL);
H A Dsvga_resource_texture.c142 void *hw, *sw; local
166 hw = sws->buffer_map(sws, st->hwbuf, usage);
167 assert(hw);
168 if (hw) {
169 memcpy(hw, sw, length);
187 hw = sws->buffer_map(sws, st->hwbuf, PIPE_TRANSFER_READ);
188 assert(hw);
189 if(hw) {
190 memcpy(sw, hw, length);
/external/mesa3d/src/gallium/drivers/svga/
H A Dsvga_pipe_misc.c54 struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer; local
59 pipe_surface_reference(&hw->cbufs[i], NULL);
63 pipe_surface_reference(&hw->zsbuf, NULL);
H A Dsvga_resource_texture.c142 void *hw, *sw; local
166 hw = sws->buffer_map(sws, st->hwbuf, usage);
167 assert(hw);
168 if (hw) {
169 memcpy(hw, sw, length);
187 hw = sws->buffer_map(sws, st->hwbuf, PIPE_TRANSFER_READ);
188 assert(hw);
189 if(hw) {
190 memcpy(sw, hw, length);
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_texstate.c595 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine ||
596 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) {
598 rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine;
599 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine;
746 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) |
754 if (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) {
755 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
760 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE;
786 uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
787 GLuint se_coord_fmt = rmesa->hw
[all...]
H A Dradeon_context.c101 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
104 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
122 rmesa->hw.zbs.dirty = 1;
123 radeon->hw.is_dirty = 1;
252 rmesa->radeon.hw.all_dirty = GL_TRUE;
H A Dradeon_common.c283 /* need to re-compute stencil hw state */
476 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) {
477 if (!radeon->hw.is_dirty)
479 foreach(atom, &radeon->hw.atomlist) {
489 foreach(atom, &radeon->hw.atomlist) {
536 if (radeon->hw.all_dirty || emitAll) {
537 foreach(atom, &radeon->hw.atomlist)
540 foreach(atom, &radeon->hw.atomlist) {
568 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw
[all...]
/external/pdfium/core/src/fxge/ge/
H A Dfx_ge_path.cpp233 FX_FLOAT hw)
237 rect.UpdateRect(end_x + hw, end_y + hw);
238 rect.UpdateRect(end_x - hw, end_y - hw);
243 point_y = end_y - hw;
245 point_y = end_y + hw;
247 rect.UpdateRect(end_x + hw, point_y);
248 rect.UpdateRect(end_x - hw, point_y);
253 point_x = end_x - hw;
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/
H A Dnv50_program.h33 uint8_t hw; /* hw index, nv50 wants flat FP inputs last */ member in struct:nv50_varying
/external/mesa3d/src/gallium/drivers/nv50/
H A Dnv50_program.h33 uint8_t hw; /* hw index, nv50 wants flat FP inputs last */ member in struct:nv50_varying

Completed in 402 milliseconds

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