Searched refs:reg (Results 1 - 25 of 119) sorted by relevance

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/art/compiler/utils/arm/
H A Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_TRUE(!reg.Overlaps(reg));
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local
32 EXPECT_TRUE(!reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsCoreRegister());
34 EXPECT_TRUE(!reg.IsSRegister());
35 EXPECT_TRUE(!reg.IsDRegister());
36 EXPECT_TRUE(!reg
69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); local
126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); local
227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); local
459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local
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/art/compiler/utils/x86/
H A Dmanaged_register_x86_test.cc25 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_TRUE(!reg.Overlaps(reg));
31 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local
32 EXPECT_TRUE(!reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsCpuRegister());
34 EXPECT_TRUE(!reg.IsXmmRegister());
35 EXPECT_TRUE(!reg.IsX87Register());
36 EXPECT_TRUE(!reg
65 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); local
91 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); local
117 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); local
255 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local
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/art/compiler/utils/x86_64/
H A Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_TRUE(!reg.Overlaps(reg));
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local
32 EXPECT_TRUE(!reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsCpuRegister());
34 EXPECT_TRUE(!reg.IsXmmRegister());
35 EXPECT_TRUE(!reg.IsX87Register());
36 EXPECT_TRUE(!reg
65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); local
91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); local
117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); local
255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local
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/art/compiler/utils/arm64/
H A Dmanaged_register_arm64_test.cc26 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); local
27 EXPECT_TRUE(reg.IsNoRegister());
28 EXPECT_TRUE(!reg.Overlaps(reg));
33 Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0); local
35 EXPECT_TRUE(!reg.IsNoRegister());
36 EXPECT_TRUE(reg.IsCoreRegister());
37 EXPECT_TRUE(!reg.IsWRegister());
38 EXPECT_TRUE(!reg.IsDRegister());
39 EXPECT_TRUE(!reg
106 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); local
169 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); local
220 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); local
387 Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0); local
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/art/runtime/arch/arm/
H A Dcontext_arm.h49 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
50 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
51 return gprs_[reg];
54 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE {
55 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
56 if (gprs_[reg] == nullptr) {
60 *val = *gprs_[reg];
65 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
67 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE {
68 DCHECK_LT(reg, static_cas
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H A Dcontext_arm.cc72 bool ArmContext::SetGPR(uint32_t reg, uintptr_t value) { argument
73 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
74 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
75 if (gprs_[reg] != nullptr) {
76 *gprs_[reg] = value;
83 bool ArmContext::SetFPR(uint32_t reg, uintptr_t value) { argument
84 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfSRegisters));
85 DCHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
86 if (fprs_[reg] != nullptr) {
87 *fprs_[reg]
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/art/runtime/arch/arm64/
H A Dcontext_arm64.h49 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
50 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
51 return gprs_[reg];
54 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE {
55 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
56 if (gprs_[reg] == nullptr) {
60 *val = *gprs_[reg];
65 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
67 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE {
68 DCHECK_LT(reg, static_cas
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/art/runtime/arch/mips/
H A Dcontext_mips.h48 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
49 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
50 return gprs_[reg];
53 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE {
54 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
55 if (gprs_[reg] == nullptr) {
59 *val = *gprs_[reg];
64 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
66 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE {
67 CHECK_LT(reg, static_cas
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H A Dcontext_mips.cc71 bool MipsContext::SetGPR(uint32_t reg, uintptr_t value) { argument
72 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
73 CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
74 if (gprs_[reg] != nullptr) {
75 *gprs_[reg] = value;
82 bool MipsContext::SetFPR(uint32_t reg, uintptr_t value) { argument
83 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFRegisters));
84 CHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
85 if (fprs_[reg] != nullptr) {
86 *fprs_[reg]
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/art/runtime/arch/x86_64/
H A Dcontext_x86_64.h47 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
48 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
49 return gprs_[reg];
52 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE {
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
54 if (gprs_[reg] == nullptr) {
58 *val = *gprs_[reg];
63 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
65 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE {
66 DCHECK_LT(reg, static_cas
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/art/test/404-optimizing-allocator/src/
H A DMain.java17 // Note that $opt$reg$ is a marker for the optimizing compiler to ensure
23 expectEquals(4, $opt$reg$TestLostCopy());
24 expectEquals(-10, $opt$reg$TestTwoLive());
25 expectEquals(-20, $opt$reg$TestThreeLive());
26 expectEquals(5, $opt$reg$TestFourLive());
27 expectEquals(10, $opt$reg$TestMultipleLive());
28 expectEquals(1, $opt$reg$TestWithBreakAndContinue());
29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7));
30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7));
31 expectEquals(-77, $opt$reg
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/art/runtime/arch/x86/
H A Dcontext_x86.h47 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
48 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
49 return gprs_[reg];
52 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE {
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
54 if (gprs_[reg] == nullptr) {
58 *val = *gprs_[reg];
63 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
65 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE {
70 bool SetFPR(uint32_t reg, uintptr_
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/art/compiler/dex/quick/
H A Dgen_loadstore.cc86 OpRegCopy(r_dest, rl_src.reg);
122 OpRegCopyWide(r_dest, rl_src.reg);
148 if (!RegClassMatches(op_kind, rl_src.reg)) {
151 OpRegCopy(new_reg, rl_src.reg);
152 // Clobber the old reg.
153 Clobber(rl_src.reg);
155 rl_src.reg = new_reg;
162 rl_src.reg = AllocTypedTemp(rl_src.fp, op_kind);
163 LoadValueDirect(rl_src, rl_src.reg);
191 if (IsLive(rl_src.reg) ||
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H A Dralloc_util.cc85 for (const RegStorage& reg : core_regs) {
86 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg));
87 m2l_->reginfo_map_.Put(reg.GetReg(), info);
90 for (const RegStorage& reg : core64_regs) {
91 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg));
92 m2l_->reginfo_map_.Put(reg.GetReg(), info);
95 for (const RegStorage& reg : sp_regs) {
96 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l
172 Clobber(RegStorage reg) argument
272 RecordCorePromotion(RegStorage reg, int s_reg) argument
305 RecordFpPromotion(RegStorage reg, int s_reg) argument
487 RegStorage reg; local
549 FreeTemp(RegStorage reg) argument
577 IsLive(RegStorage reg) argument
591 IsTemp(RegStorage reg) argument
604 IsPromoted(RegStorage reg) argument
617 IsDirty(RegStorage reg) argument
635 LockTemp(RegStorage reg) argument
651 ResetDef(RegStorage reg) argument
660 NullifyRange(RegStorage reg, int s_reg) argument
743 FlushRegWide(RegStorage reg) argument
763 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); local
771 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); local
776 FlushReg(RegStorage reg) argument
783 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, kWord, kNotVolatile); local
807 RegClassMatches(int reg_class, RegStorage reg) argument
822 RegStorage reg = loc.reg; local
866 MarkTemp(RegStorage reg) argument
873 UnmarkTemp(RegStorage reg) argument
880 MarkWide(RegStorage reg) argument
902 MarkNarrow(RegStorage reg) argument
938 MarkInUse(RegStorage reg) argument
1014 RegStorage reg = AllocLiveReg(loc.s_reg_low, loc.ref ? kRefReg : kAnyReg, false); local
1039 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, true); local
1276 RegStorage reg = RegStorage::InvalidReg(); local
1306 RegStorage reg = AllocPreservedCoreReg(low_sreg); local
1320 RegStorage reg = RegStorage::InvalidReg(); local
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/art/runtime/entrypoints/portable/
H A Dportable_thread_entrypoints.cc41 for (size_t reg = 0; reg < num_regs; ++reg) {
42 if (TestBitmap(reg, reg_bitmap)) {
43 new_frame->SetVRegReference(reg, cur_frame->GetVRegReference(reg));
45 new_frame->SetVReg(reg, cur_frame->GetVReg(reg));
64 static bool TestBitmap(int reg, const uint8_t* reg_vector) { argument
65 return ((reg_vector[reg /
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/art/compiler/dex/quick/x86/
H A Dfp_x86.cc63 RegStorage r_dest = rl_result.reg;
64 RegStorage r_src1 = rl_src1.reg;
65 RegStorage r_src2 = rl_src2.reg;
116 if (rl_result.reg == rl_src2.reg) {
117 rl_src2.reg = AllocTempDouble();
118 OpRegCopy(rl_src2.reg, rl_result.reg);
120 OpRegCopy(rl_result.reg, rl_src1.reg);
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H A Dint_x86.cc41 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
42 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0
44 NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg());
45 NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg());
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, argument
108 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode
109 NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg
919 IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) argument
1073 OpPcRelLoad(RegStorage reg, LIR* target) argument
1120 GenDivZeroCheckWide(RegStorage reg) argument
1236 OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) argument
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/art/runtime/arch/
H A Dcontext.h53 virtual uintptr_t* GetGPRAddress(uint32_t reg) = 0;
57 virtual bool GetGPR(uint32_t reg, uintptr_t* val) = 0;
61 virtual bool SetGPR(uint32_t reg, uintptr_t value) = 0;
65 virtual bool GetFPR(uint32_t reg, uintptr_t* val) = 0;
69 virtual bool SetFPR(uint32_t reg, uintptr_t value) = 0;
/art/compiler/dex/quick/arm/
H A Dint_arm.cc129 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh());
132 OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow());
146 rl_temp.reg.SetReg(t_reg.GetReg());
164 RegStorage low_reg = rl_src1.reg.GetLow();
165 RegStorage high_reg = rl_src1.reg.GetHigh();
251 OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val);
254 LoadConstant(rl_result.reg, false_va
367 OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) argument
1055 OpPcRelLoad(RegStorage reg, LIR* target) argument
1077 GenDivZeroCheckWide(RegStorage reg) argument
1102 OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) argument
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H A Dfp_arm.cc65 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
112 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
142 RegisterInfo* info = GetRegInfo(rl_src.reg);
152 NewLIR2(kThumb2VcvtF64U32, rl_result.reg.GetReg(), src_low.GetReg());
154 NewLIR3(kThumb2VmlaF64, rl_result.reg.GetReg(), tmp1.GetReg(), tmp2.GetReg());
165 RegisterInfo* info = GetRegInfo(rl_src.reg);
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/art/compiler/dex/
H A Dreg_location.h52 RegStorage reg; // Encoded physical registers. member in struct:art::RegLocation
H A Dreg_storage.h99 static const uint16_t kHighRegNumMask = 0x001f; // 0..31 for high reg
107 constexpr RegStorage(RegStorageKind rs_kind, int reg) argument
111 kValid | rs_kind | (reg & kRegTypeMask)) {
119 << "High reg must be in 0..31: " << high_reg, false)
126 // We do not provide a general operator overload for equality of reg storage, as this is
183 static constexpr bool IsFloat(uint16_t reg) { argument
184 return ((reg & kFloatingPoint) == kFloatingPoint);
187 static constexpr bool IsDouble(uint16_t reg) { argument
188 return (reg & (kFloatingPoint | k64BitMask)) == (kFloatingPoint | k64Bits);
191 static constexpr bool IsSingle(uint16_t reg) { argument
195 Is32Bit(uint16_t reg) argument
199 Is64Bit(uint16_t reg) argument
203 Is64BitSolo(uint16_t reg) argument
214 SetReg(int reg) argument
221 SetLowReg(int reg) argument
250 SetHighReg(int reg) argument
[all...]
/art/compiler/dex/quick/mips/
H A Dint_mips.cc51 NewLIR3(kMipsSlt, t0.GetReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg());
52 NewLIR3(kMipsSlt, t1.GetReg(), rl_src2.reg.GetHighReg(), rl_src1.reg.GetHighReg());
53 NewLIR3(kMipsSubu, rl_result.reg.GetReg(), t1.GetReg(), t0.GetReg());
54 LIR* branch = OpCmpImmBranch(kCondNe, rl_result.reg, 0, NULL);
55 NewLIR3(kMipsSltu, t0.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg());
56 NewLIR3(kMipsSltu, t1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg
131 OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) argument
327 OpPcRelLoad(RegStorage reg, LIR* target) argument
354 GenDivZeroCheckWide(RegStorage reg) argument
369 OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) argument
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/art/compiler/dex/quick/arm64/
H A Dfp_arm64.cc62 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
115 NewLIR3(FWIDE(op), rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
192 NewLIR2(op, rl_result.reg.GetReg(), rl_src.reg.GetReg());
211 NewLIR2(FWIDE(kA64Fcmp2ff), rl_src1.reg.GetReg(), rl_src2.reg
[all...]
/art/compiler/optimizing/
H A Doptimizing_unit_test.h42 int reg = -1) {
47 interval->SetRegister(reg);

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