| /system/core/libpixelflinger/codeflinger/ |
| H A D | load_store.cpp | 84 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 8));
86 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 16));
91 ORR(AL, 0, s1, s1, reg_imm(s0, LSL, 8));
93 ORR(AL, 0, s.reg, s1, reg_imm(s0, LSL, 16));
141 MOV(AL, 0, d.reg, reg_imm(s, LSL, 32-h));
217 RSB(AL, 0, d, s, reg_imm(s, LSL, dbits));
223 MOV(AL, 0, d, reg_imm(s, LSL, dbits-sbits));
237 ORR(AL, 0, d, s, reg_imm(s, LSL, sbits));
315 MOV(AL, 0, ireg, reg_imm(s.reg, LSL, 32-sh));
353 else if (shift<0) ADD(AL, 0, ireg, ireg, reg_imm(dither.reg, LSL,
[all...] |
| H A D | texturing.cpp | 543 MOV(GE, 0, width, reg_imm(width, LSL, shift));
560 MOV(LE, 0, u, reg_imm(width, LSL, FRAC_BITS));
578 MOV(GE, 0, height, reg_imm(height, LSL, shift));
584 MOV(LE, 0, v, reg_imm(height, LSL, FRAC_BITS));
587 MOV(GT, 0, height, reg_imm(stride, LSL, shift));
834 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift));
849 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift));
863 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift));
876 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift));
922 MOV(AL, 0, U, reg_imm(U, LSL, prescal
[all...] |
| H A D | GGLAssembler.cpp | 380 ADD(AL, 0, tx, tx, reg_imm(ty, LSL, GGL_DITHER_ORDER_SHIFT));
381 ORR(AL, 0, parts.count.reg, tx, reg_imm(parts.count.reg, LSL, 16));
385 MOV(AL, 0, parts.count.reg, reg_imm(parts.count.reg, LSL, 16));
434 ADDR_ADD(AL, 0, zbase, zbase, reg_imm(Rs, LSL, 1));
449 ADDR_ADD(AL, 0, parts.covPtr.reg, parts.covPtr.reg, reg_imm(Rx, LSL, 1));
688 MOV(AL, 0, fragment.reg, reg_imm(incoming.reg, LSL, 1));
997 ADDR_ADD(AL, 0, d.reg, b.reg, reg_imm(o.reg, LSL, 2));
1001 ADDR_ADD(AL, 0, d.reg, b.reg, reg_imm(o.reg, LSL, 1));
1004 ADDR_ADD(AL, 0, d.reg, o.reg, reg_imm(o.reg, LSL, 1));
1009 ADDR_ADD(AL, 0, d.reg, b.reg, reg_imm(o.reg, LSL,
[all...] |
| H A D | blending.cpp | 448 else if (shift<0) RSB(AL, 0, diff.reg, fb.reg, reg_imm(fragment.reg, LSL,-shift));
466 else if (shift<0) SUB(AL, 0, diff.reg, fb.reg, reg_imm(fragment.reg, LSL,-shift));
619 ADD(AL, 0, d.reg, temp, reg_imm(add.reg, LSL, ms-as));
643 ADD(AL, 0, d.reg, src.reg, reg_imm(dst.reg, LSL, shift));
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| H A D | MIPSAssembler.cpp | 397 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
508 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
540 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
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| H A D | ARMAssemblerInterface.h | 43 LSL, LSR, ASR, ROR enumerator in enum:android::ARMAssemblerInterface::__anon165
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| H A D | Arm64Assembler.cpp | 157 "LSL", "LSR", "ASR", "ROR"
470 if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_type == LSL)
1085 LOG_INSTR("ADD X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift);
1092 LOG_INSTR("SUB X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift);
1180 LOG_INSTR("MOVZ X%d, #0x%x, LSL #%d\n", Rd, imm, shift);
1187 LOG_INSTR("MOVK W%d, #0x%x, LSL #%d\n", Rd, imm, shift);
1194 LOG_INSTR("MOVZ W%d, #0x%x, LSL #%d\n", Rd, imm, shift);
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